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PDF LC01707PLF Data sheet ( Hoja de datos )

Número de pieza LC01707PLF
Descripción FM multiple tuner IC
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No Preview Available ! LC01707PLF Hoja de datos, Descripción, Manual

Ordering number : ENA1928B
LC01707PLF
CMOS LSI
FM multiple tuner IC
http://onsemi.com
Overview
LC01707PLF is a vehicle-mounted FM multiple tuner IC with FM-FE, IF, IF-Filter, PLL, FM-DEMO and LPF
incorporated. An FM multiple tuner can be developed with this one chip. It makes up a small-sized FM multiple tuners
which can be mounted on PND.
Functions
It is the FM tuner IC exclusively for the FM multiple.
LNA is incorporated
Image reduction complex BPF is incorporated
Wide / Narrow Band RF AGC is incorporated
Narrow Band IF AGC is incorporated
Image rejection is adopted
DLL detection method is adopted for the FM detection circuit, and it is not necessary to adjust.
LPF for the carrier removal is incorporated.
IC requires fewer external components.
It is a BUS control tuner IC which can be controlled by controlled by I2C BUS.
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Supply voltage
Maximum input voltage
Maximum output voltage
Power dissipation
VDD max
VDD H
VDD L
Pd max
Ta = 85°C *1
Operating ambient
Topr
Storage temperature
Tstg
Maximum junction temperature Tj max
*1: Board size: 80mm × 70mm × 1.6mm Glass epoxy double-sided board
Ratings
4.3
4.3
4.3
700
-40 to 85
-55 to 150
150
Unit
V
V
V
mW
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
32812 SY/O1911 SY/81011 SY 20110210-S00002 No.A1928-1/18

1 page




LC01707PLF pdf
Pin Function
LC01707PLF
Pin No. Pin name
Function
1 NAGC
Narrow band AGC detection capacitor connection pin.
Equivalent circuit
VDD
VDD
1
2 WAGC Wide band AGC detection capacitor connection pin.
3 VSS
4 NC
5 NC
6 VDD
7 LNA_P
8 VSS
9 LNA_N
GND pin for IF.
No connection.
No connection.
Supply pin for LNA.
Pin 7 is + input pin for LNA.
Pin 8 is GND pin for LNA.
Pin 9 is - input pin for LNA.
10 NC
11 NC
12 VSS
13 CP
No connection.
No connection.
GND pin 1st mixer for the 1st mixer.
PLL charge pump capacitor connection pin.
14 VDD
15 VDD
Supply pin for the 1st mixer.
Supply pin for local oscillator.
VDD
VDD
2
VDD VDD
7
9
VDD
VDD
13
VDD
VDD
Continued on next page.
No.A1928-5/18

5 Page





LC01707PLF arduino
LC01707PLF
Electrical specification and timing for I/O stages
t1
SD
SC
t10
t5
START
condition
t2
t4 t2
t7 t1
t6 t3
t9
t8
STOP
condition
Bus line characteristics
Characteristic
SCL clock frequency
Fall time of SDA and SCL
Rise time of SDA and SCL
SCL “H” time
SCL “L” time
[Start] condition holding time
Data holding time for I2C bus device
Data setup time
[Stop] condition setup time
Bus free time between [Stop] and [Start]
[Start] condition setup time
Bus line capacitive load
Symbol
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Cb
FAST-MODE
min max
20+0.1Cb
20+0.1Cb
0.6
1.3
0.6
0.3
0.1
0.6
1.3
0.6
400
300
300
400
unit
kHz
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
pF
Serial interface voltage level
VDD: Communication bus voltage
Characteristic
min
High level input voltage
Low level input voltage
0.7VDD
0.0
High level output voltage (open drain)
Low level output voltage (open drain)
VDD *2
0.0
*2: Output impedance of open drain becomes high at the high level output voltage.
Output voltage equals to VDD (voltage =VDD) since drain is pulled up to VDD.
max
VDD
0.3VDD
0.2VDD
unit
V
V
V
V
Example at
SCL = 100kHz
100
3
7
10
3
10
20
No.A1928-11/18

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