PDF UCD4015B Data sheet ( Hoja de datos )

Número de pieza	UCD4015B
Descripción	CMOS Dual 4-Stage Static Shift Register
Fabricantes	Unisonic Technologies
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No Preview Available ! UNISONIC TECHNOLOGIES CO., LTD UCD4015B Preliminary CMOS Dual 4-Stage Static Shift Register CMOS IC DESCRIPTION UCD4015B consists of two identical,independent,4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET input as well as a single serial DATA input. ”Q” outputs are available from each of the four stages on both registers. All registers stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one UCD4015 package or to more than 8 stages using additional UCD4015’s is possible. FEATURES * 12MHz (typ.) clock rate at 10V * Maximum input current of 1μA at 18V * Fully static operation * 8 master-slave flip-flops plus input and output buffering APPLICATIONS * General-purpose register * Serial-input/parallel-output data queueing * Serial to parallel data conversion ORDERING INFORMATION Ordering Number Lead Free Halogen Free UCD4015BL-S16-T UCD4015BG-S16-T UCD4015BL-S16-R UCD4015BG-S16-R UCD4015BL-P16-T UCD4015BG-P16-T UCD4015BL-P16-R UCD4015BG-P16-R Package SOP-16 SOP-16 TSSOP-16 TSSOP-16 SOP-16 TSSOP-16 Packing Tube Tape Reel Tube Tape Reel www.unisonic.com.tw Copyright © 2013 Unisonic Technologies Co., Ltd 1 of 8 QW-R502-875.b 1 page UCD4015B Preliminary CMOS IC ELECTRICAL CHARACTERISTICS(Cont.) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current SYMBOL TEST CONDITIONS VOUT=0.5, 4.5V, VDD=5V VIL VOUT=1, 9V, VDD=10V VOUT=1.5, 13.5V, VDD=15V VOUT=0.5, 4.5V, VDD=5V VIH VOUT=1, 9V, VDD=10V VOUT=1.5, 13.5V, VDD=15V II(LEAK) VIN =0, 18V, VDD=18V MIN TYP MAX UNIT 1.5 3V 4 3.5 7V 11 ±0.1 μA SWITCHING CHARACTERISTICS (TA =25°C, Input tr, tf =20ns, CL =50pF, RL = 200KΩ) PARAMETER CLOCKED OPERATION Propagation Delay Time Transition Time Maximum Clock Input Frequency Minimum Clock Pulse Width Clock Rise and Fall Time Minimum Data Setup Time Minimum Data Hold Timel Average Input Capacitance RESET OPERATION Propagation Delay Time Minimum Reset Pulse Width SYMBOL TEST CONDITIONS VDD=5V tPLH / tPHL VDD=10V VDD=15V VDD=5V tTHL/ tTLH VDD=10V VDD=15V VDD=5V fCL VDD=10V VDD=15V VDD=5V tWCL VDD=10V VDD=15 VDD=5V trCL / tfCL VDD=10V VDD=15V VDD=5V tSU VDD=10V VDD=15V VDD=5V tH VDD=10V VDD=15V CI Any Input VDD=5V tPLH / tPHL VDD=10V VDD=15V VDD=5V tWR VDD=10V VDD=15 MIN TYP MAX UNIT 160 320 80 160 ns 60 120 100 200 50 100 ns 40 80 36 6 12 MHz 8.5 17 90 180 40 80 ns 25 50 15 6 μs 2 35 70 20 40 ns 15 30 0 0 ns 0 5 7.5 pF 200 400 100 200 ns 80 160 100 200 40 80 ns 30 60 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 8 QW-R502-875.b 5 Page

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