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PDF ICS87001I-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS87001I-01 | |
| Descripción | LVCMOS/LVTTL Clock Divider | |
| Fabricantes | Integrated Device Technology | |
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LVCMOS/LVTTL Clock Divider
ICS87001I-01
DATA SHEET
General Description
The ICS87001I-01 is a low skew, ÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷8, ÷16
LVCMOS/LVTTL Clock Divider. The ICS87001I-01 has selectable
clock inputs that accept single ended input levels. Output enable pin
controls whether the output is in the active or high impedance state.
The ICS87001I-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001I-01 ideal for those applications demanding well defined
performance and repeatability.
Features
• One LVCMOS / LVTTL output
• Selectable LVCMOS / LVTTL clock inputs
• Maximum output frequency: 250MHz
• Part-to-part skew: 135ps (typical)
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL Pulldown
CLK0
Pulldown 0
CLK1
Pulldown 1
N2:N0 Pulldown
OE Pullup
3
N Output Divider
N2:N0
0 0 0 ÷1 (default)
0 0 1 ÷2
0 1 0 ÷3
0 1 1 ÷4
1 0 0 ÷5
1 0 1 ÷6
1 1 0 ÷8
1 1 1 ÷16
Q
Pin Assignment
OE
VDD
CLK0
CLK_SEL
CLK1
N2
N1
N0
1
2
3
4
5
6
7
8
16 VDDO
15 nc
14 Q
13 nc
12 GND
11 nc
10 nc
9 GND
ICS87001I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
ICS87001BGI-01 REVISION A JANUARY 23, 2013
1
©2013 Integrated Device Technology, Inc.
1 page  
ICS87001I-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
fOUT
tPD
Output Frequency
Propagation Delay,
Low to High; NOTE 1
N2
N>2
3.6
4.3
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
0.4
40
tEN Output Enable Time
tDIS Output Disable Time
Typical
4.6
5.5
0.6
Maximum
250
5.7
6.7
750
1.0
60
10
10
Units
MHz
ns
ns
ps
ns
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fIN 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
fOUT
tPD
Output Frequency
Propagation Delay,
Low to High; NOTE 1
N2
N>2
3.5
4.5
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
0.4
40
tEN Output Enable Time
tDIS Output Disable Time
Typical
4.8
5.7
0.7
Maximum
250
6.2
6.9
590
1.1
60
10
10
Units
MHz
ns
ns
ps
ns
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fIN 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ICS87001BGI-01 REVISION A JANUARY 23, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
ICS87001I-01 Data Sheet
Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
LVCMOS/LVTTL CLOCK DIVIDER
1
96.0°C/W
2.5
93.9°C/W
ICS87001BGI-01 REVISION A JANUARY 23, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
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