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PDF CH7304 Data sheet ( Hoja de datos )
| Número de pieza | CH7304 | |
| Descripción | Single LVDS Transmitter | |
| Fabricantes | Chrontel | |
| Logotipo |  |
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Chrontel
CH7304
CH7304 Single LVDS Transmitter
Features
• Single LVDS transmitter
• Supports pixel rate up to 100M pixels/sec
• Supports up to SXGA resolution (1280 x 1024)
• LVDS low jitter PLL
• LVDS 18-bit output
• 2D dither engine
• Panel protection and power down sequencing
• Programmable power management
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 64-pin LQFP package
General Description
The CH7304 is a Display Controller device, which accepts
a graphics data stream over one 12-bit wide variable
voltage (1.1V to 3.3V) port. The data stream outputs
through an LVDS transmitter to an LCD panel. A
maximum of 100M pixels per second can be output
through a single LVDS link.
The LVDS transmitter includes a programmable dither
function for support of 18-bit panels. Data is encoded into
commonly used formats, including those detailed in the
OpenLDI and the SPWG specification. Serialized data
output on four differential channels.
XCLK,XCLK*
2
H,V, DE
3
D[11:0]
12
VREF
Clock,
Data,
Sync
Latch &
Demux
Color
Space
Conversion
LVDS PLL
Dither
Engine
LVDS
Encode /
Serialize
Serial Port Control and Misc. Functions
LVDS
Transmit
LDC[3:0],LDC*[3:0]
6 LLC,LLC*
2
2
ENAVDD, ENABKL
XTAL
2 XI/FIN,XO
Figure 1: Functional Block Diagram
201-0000-053 Rev. 1.31, 6/14/2006
1
1 page  
CHRONTEL
CH7304
Table 1: Pin Description (continued)
Pin #
# of Pins Type
50-55, 58-63 12
In
Symbol
D[11:0]
56, 57 2 In XCLK,
XCLK*
42, 64
35, 49
48
5,11,22,28
8,14,19,25,31
38
36
2
2
1
4
5
1
1
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
VDDV
LVDD
LGND
LPLL_VDD
LPLL_GND
Description
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF is the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the device for use with
the H, V and D[11:0] data. If differential clocks are not available, the
XCLK* input should be connected to VREF. The clock polarity can be
selected by the MCP control bit (Register 1Ch).
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (1.1V to 3.3V)
LVDS Supply Voltage (3.3V)
LVDS Ground
LVDS PLL Supply Voltage (3.3V)
LVDS PLL Ground
201-0000-053 Rev. 1.31, 6/14/2006
5
5 Page 
CHRONTEL
XCLK
LVDS
PLL
XCLK
FIFO
LOCK
LOCK DETECT
LOCKST
LPFORC
0
MUX
1
LPLEN
HSYNC
VSYNC
SYNC
DETECT
Register 66h
PANEN
LSYNCEN
LPLOCK
LPFORC
LPLEN
BKLEN
SYNCST
Note:
1) LOCKST will be logic
low if either XCLK or the
LVDS PLL output is
unstable.
2) SYNCST will be logic
low if either Hsync or
Vsync is unstable or
missing.
CH7304
LSYNCEN
XCLK
XCLK
Detect
FOSC (from oscillator)
CLKDETD
Reg. 14h [2]
Power Sequencing
ENAVDD
ENABKL
Figure 6: Detection Circuits for Panel Protection
The power up sequence can occur only if (a) XCLK is not missing, (b) there are no missing HSYNC and VSYNC, (c)
the PLL CLOCK is stable, and (d) PANEN is set to 1. The power down sequence happens if any of those conditions fails.
The power up sequence can also occur if the panel protection circuitry is bypassed.
The panel protection circuitry is comprised of a LOCKDET block, which detects an unstable clock from the LVDS PLL,
a SYNCDET block, which detects missing inputs HSYNC and VSYNC and an XCLK Detect block which detects
missing XCLK. XCLK stability (assuming it is not missing) is determined by the number of PLL unlock signals
generated within one frame. This number is programmable via serial port using the BGLMT register (Register 7Fh).
The SYNCDET block consists of counters to count HSYNC and VSYNC pulses. One counter is used to count the
number of HSYNC pulses per frame over 3 frames. The end counts for all 3 frames must be equal to enable the power up
sequence. In addition, the SYNCDET block checks for the presence of VSYNC and HSYNC. If VSYNC is missing for 2
frames or if HSYNC is missing for 32us the power up sequence is disabled.
The XCLK Detect block detects if XCLK is missing for more than approximately 1.2us.
201-0000-053 Rev. 1.31, 6/14/2006
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CH7304.PDF ] | |
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