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PDF EM44DM0888LBA Data sheet ( Hoja de datos )
| Número de pieza | EM44DM0888LBA | |
| Descripción | Double DATA RATE SDRAM | |
| Fabricantes | Eorex | |
| Logotipo |  |
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Revision History
Revision 0.1 (Feb. 2011)
-First release.
Revision 0.2 (Jan.2013)
-Add speed 1066.
EM44DM0888LBA
Feb. 2012
1/29
www.eorex.com
1 page  
EM44DM0888LBA
Pin Description (Simplified)
Pin
E8,F8
G8
F2
H8,H3,H7,J2,
J8,J3,J7,K2,
K8,K3,H2,K7,
L2,L8
G2,G3,G1
F9
F7, G7, F3
Name
Function
CK,/CK
/CS
(System Clock)
CK and /CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and
negative edge of /CK. Output (read) data is referenced to the
crossings of CK and /CK (both directions of crossing).
(Chip Select)
All commands are masked when CS is registered HIGH. CS provides
for external Rank selection on systems with multiple Ranks. CS is
considered part of the command code.
CKE
A0~A13
BA0, BA1,BA2
ODT
/RAS,/CAS,/WE
(Clock Enable)
CKE high activates and CKE low deactivates internal clock signals and
device input buffers and output drivers. Taking CKE low provides
Precharge Power-Down and Self- Refresh operation (all banks idle), or
Active Power-Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for Self-Refresh entry. CKE is
asynchronous for Self-Refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, /CK,
ODT and CKE are disabled during Power Down. Input buffers,
excluding CKE are disabled during Self-Refresh.
(Address)
Provided the row address (RA0 – RA13) for Active commands and the
column address (CA0-CA9) and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA0, BA1 & BA2. The address inputs also provide the
op-code during Mode Register Set commands.
(Bank Address)
BA0 – BA2 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode
register or extended mode register is to be accessed during a MRS or
EMRS cycle.
(On Die Termination)
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is applied to each DQ,
UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will
be ignored if the Extended Mode Register (EMRS(1)) is programmed
to disable ODT.
(Command Inputs)
/RAS, /CAS and /WE (along with /CS) define the command being
entered.
Feb. 2012
5/29
www.eorex.com
5 Page 
OCD Default Setting Table
Parameter
Output Impedance
Pull-up / Pull-down mismatch
Output Slew Rate
Output Impedance Step Size for OCD Calibration
EM44DM0888LBA
Min. Typ.
12.6 18
0-
1.5 -
0-
Max.
23.4
4
5.0
1.5
Units
Ω
Ω
V/ns
Ω
AC Operating Test Conditions
(VDD=1.8V±0.1V)
Symbol
VSWING (max.)
SLEW
VREF
Parameter
Input Signal Maximum Peak to Peak Swing
Input Signal Minimum Slew Rate
Input Reference Level
Value
1.0
1.0
0.5*VDDQ
Units
V
V/ns
V
AC Operating Test Conditions
Symbol
VID
VIX
VOX
VIH
VIL
Parameter
AC Differential Input Voltage
AC Differential Cross Point Input Voltage
AC Differential Cross Point Output Voltage
Input Logic High Voltage
Input Logic High Voltage
Min.
0.5
0.5*VDDQ-0.175
0.5*VDDQ-0.125
VREF+0.200
VSSQ-Vpeak
Max.
VDDQ
0.5*VDDQ+0.175
0.5*VDDQ+0.125
VDDQ+Vpeak
VREF-0.200
Units
V
V
V
V
V
Feb. 2012
11/29
www.eorex.com
11 Page | ||
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| PDF Descargar | [ Datasheet EM44DM0888LBA.PDF ] | |
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