SB3229 Datasheet PDF - ON Semiconductor
| Part Number | SB3229 | |
| Description | Preconfigured DSP System | |
| Manufacturers | ON Semiconductor | |
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RHYTHM SB3229
Preconfigured DSP System
for Hearings Aids
Description
The RHYTHMt SB3229 hybrid from ON Semiconductor is
a trimmer−configurable DSP system based on a four−channel
compression circuit featuring a feedback cancellation algorithm.
Based on a phase cancellation method, SB3229’s adaptive feedback
reduction algorithm provides added stable gain to enable extra gain
and user comfort. It features rapid adjustment for dynamic feedback
situations and resistance to tonal inputs.
In addition to these adaptive algorithms, SB3229 also supports the
following features: up to four channel WDRC, low−distortion
compression limiting, cross fading between audio paths for click−free
memory changes, eight−band graphic equalizer, eight configurable
generic biquad filters, programming speed enhancements, in−channel
squelch to attenuate microphone and circuit noise in quiet
environments, optional peak clipping, flexible compression
adjustments, volume control, rocker switch, noise generation for
Tinnitus treatment, and industry−leading security features to avoid
cloning and software piracy.
A trimmer interface supports manual circuit configuration. It
continuously monitors trimmer positions and translates them into
the hearing−aid parameters of choice. A Serial Data or I2C Interface
provides full programmability at the factory and in the field.
The SB3229 hybrid contains a 256 kbit EEPROM intended for
programmable and trimmer based devices.
Features
• Adaptive Feedback Cancellation
• WDRC Compression with Choice of 1, 2 or 4 Channels of
Compression
• Auto Telecoil with Programmable Delay
• EVOKE LITEt Acoustic Indicators
• Noise Generator for Tinnitus Treatment or In−Situ Audiometry
• Frequency Response Shaping with Graphic EQ
• Trimmer Compatibility – Four Three−Terminal Trimmers with
Configurable Assignments of Control Parameters
• I2C and SDA Programming
• Rocker Switch Support for Memory Change and/or Volume Control
Adjustment
• Support for Active Hi or Active Lo Switching
• Analog or Digital Volume Control with Programmable Range
• High Quality 20−bit Audio Processing
• High Power/High Gain Capability
• SOUNDFIT Fitting Software
• Configurable Low Battery Indicator
www.onsemi.com
25 PAD
HYBRID
CASE 127DN
PAD CONNECTION
VIN2 17
TIN 16
DAI 15
VC 14
D_VC 13
SDA 12
CLK 11
18
VIN1
19
TR4
20
TR3
21
TR2
22
TR1
23
N/C
25 24
1 VREG
2 MGND
3 GND
4 PGND
5 OUT+
6 OUT−
7 VBP
MS1 10
9
8
MS2
(Bottom View)
VB
MARKING DIAGRAM
SB3229−E1
XXXXXX
SB3229 = Specific Device Code
E1 = RoHS Compliant Hybrid
XXXXXX = Work Order Number
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 5
1
Publication Order Number:
SB3229/D
|
| |
 
RHYTHM SB3229
Table 3. I2C TIMING
Standard Mode
Fast Mode
Parameter
Symbol
Min
Max
Min
Max Units
Clock Frequency
fPC_CLK
0
100
0
400 kHz
Hold time (repeated) START condition. After this
tHD;STA
4.0
−
0.6
− msec
period, the first clock pulse is generated.
LOW Period of the PC_CLK Clock
HIGH Period of the PC_CLK Clock
Set−up time for a repeated START condition
Data Hold Time:
for CBUS Compatible Masters
for I2C−bus Devices
tLOW
tHIGH
tSU;STA
tHD;DAT
4.7
4.0
4.7
5.0
0
(Note 1)
−
−
−
−
3.4
(Note 2)
−
−
−
−
0
(Note 1)
−
−
−
−
0.9
(Note 2)
msec
msec
msec
msec
Data set−up time
Rise time of both PC_SDA and PC_CLK signals
tSU;DAT
tr
250
−
−
1000
100
20 + 0.1 Cb
(Note 4)
−
300
nsec
nsec
Fall time of both PC_SDA and PC_CLK signals
tf
−
300 20 + 0.1 Cb 300
nsec
(Note 4)
Set−up time for STOP condition
Bus free time between a STOP and START condition
Output fall time from VIHmin to VILmax with a bus
capacitance from 10 pF to 400 pF
tSU;STO
tBUF
tof
4.0
4.7
−
− 0.6 −
− 1.3 −
250 20 + 0.1 Cb 250
(Note 4)
nsec
msec
nsec
Pulse width of spikes which must be suppressed by
tSP
n/a
n/a
0
50 nsec
the input filter
Capacitive load for each bus line
Cb − 400 − 400 pF
1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.
2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the PC_CLK signal.
3. A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT P250ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the
LOW period of the PC_CLK signal, it must output the next data bit to the PC_SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard−mode I2C−bus specification) before the PC_CLK line is released.
4. Cb = total capacitance of one bus line in pF.
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| Information | Total 17 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ SB3229.PDF Datasheet ] | |
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