PDF LV4904V Data sheet ( Hoja de datos )

Número de pieza	LV4904V
Descripción	Digital Input Class-D Power Amplifier
Fabricantes	ON Semiconductor
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No Preview Available ! Ordering number: ENA1963 LV4904V Monolithic IC Digital Input Class-D Power Amplifier http://onsemi.com Overview The LV4904V is a 2-channel class-D amplifier IC that supports digital input. With this single chip and with a minimal number of external components, it is possible to effectively implement class-D amplifiers. The LV4904V incorporates a soft mute function and a gain controller without pop noise, and can be used as a master volume control of the set. Its function settings can be established through an I2C bus interface, but it is also possible to establish these settings simply by pin settings without using the I2C bus. The LV4904V is ideally suited as the power amplifiers in mini components, flat-panel TVs, game machines, electronic musical instruments and other such products. Features • I2S input, 2-channel class-D power amplifier • On-chip variable over-sampler • Gain controller (+12dB to -81dB, in 1.5 dB increments) • Soft mute function • Controllable via I2C bus or pin settings • Under voltage protection circuit, overcurrent protection circuit, thermal protection circuit integrated Functions • Input PCM (Fs): 32 kHz/44.1 kHz/48 kHz/88.1 kHz/96 kHz/176.2 kHz/192 kHz • Master clock input: 256 fs/384 fs/512 fs/768 fs (when Fs=32/44.1/48 kHz) • Input format: I2S/24 bits left justified MSB-first / 24 bits right justified LSB-first / 16/18/20/24 bits right justified MSB-first • Output (THD + N=10%) : 10W × 2 channels (PVD = 15V, RL = 8Ω), 15W × 2 channels (PVD = 18V, RL = 8Ω) • Efficiency : 85% (PVD = 15V, RL = 8Ω, fin = 1 kHz, Po = 10W) • THD + N : 0.1% or less (PVD = 15V, RL = 8Ω, fin = 1 kHz, Po = 1W, filter: AES17) • Power supply voltages : PVD = 8 to 20V, VDD = 3.3V Semiconductor Components Industries, LLC, 2013 May, 2013 92811 SY 20110606-S00002 No.A1963-1/30 1 page Block Diagram RSTB 1 VDD 12 13 VSS 33 VDD 32 VSS 4 BCK 5 LRCK 6 SDIN MCK 3 2 ENABLE 7 DFORM0 8 DFORM1 9 DFORM2 10 MCKFS 11 SRATE 42 GAIN0 41 GAIN1 40 GAIN2 39 GAIN3 38 GAIN4 37 GAIN5 36 MUTEB 35 MODE 34 TEST 43 SDA 44 SCL CONTROLLER I2C I/F LV4904V PWM RECEIVER PWM RECEIVER CONTROL DELAY SEQUENCE PVD1 30 OUTPUT STAGE CH1+ OUT_CH1_P 29 BOOT_CH1_P 28 OUTPUT STAGE CH1- BOOT_CH1_N 26 OUT_CH1_N 25 THERMAL PGND1 24 PGND1 23 OVER CURRENT PGND2 22 PGND2 21 PWM RECEIVER PWM RECEIVER VSS CONTROL DELAY PGND1 PGND2 OUTPUT STAGE CH2- OUT_CH2_N 20 BOOT_CH2_N 19 OUTPUT STAGE CH2+ BOOT_CH2_P 17 OUT_CH2_P 16 PVD2 15 REGULATOR (5V) VDDA1 27 VDDA2 18 PTAB1 31 PTAB2 14 No.A1963-5/25 5 Page LV4904V 2.9 Gain setting pins (GAIN0, GAIN1, GAIN2, GAIN3, GAIN4, GAIN5) The gain can be set by setting the GAIN0 to GAIN5 pins to high or low. In the combined I2C bus and pin setting mode, the gain settings (Table 8.2.1) established according to the I2C register are valid when all the GAIN0 to GAIN5 pins are low. Since the initial setting of the I2C register is in mute state, mute is the setting that is established when GAIN0 to GAIN5 are low in the initial state after reset release. Table 2.9 shows the gain settings established according to the GAIN0 to GAIN5 pins. The gain settings established according to the pin 6 bits and the gain settings established according to the register 6 bits are identical, so refer to Table 8.2.1 for the detailed settings. GAIN5 H H H … H H H … L L L GAIN4 H H H … H H H … L L L GAIN3 H H H … H L L … L L L GAIN2 H H H … L H H … L L L Table 2.9 Gain settings GAIN1 GAIN0 Gain Setting Combined I2C Bus and Pin setting mode Pin Setting Mode HH +12.0dB HL +10.5dB LH +9.0dB …… (settings in increments of 1.5dB) LL +1.5dB HH HL 0dB -1.5dB …… (settings in increments of 1.5dB) HL -79.5dB LH LL -81.0dB I2C register settings Mute 2.10 Mute pin (MUTEB) MUTEB is the low active soft mute pin that controls both the left and right channels. In the combined I2C bus and pin setting mode, the mute setting (Table 8.2.2) established according to the I2C register is valid when MUTEB is low. Since the initial setting of the I2C register is in mute state, mute is the setting that is established when MUTEB is low in the initial state after reset release. Table 2.10 shows the MUTEB function settings. MUTEB L H Table 2.10 MUTEB pin function settings Setting Combined I2C Bus and Pin setting mode I2C register setting Pin Setting Mode Mute ON Mute OFF 2.11 Test mode setting pins (TEST, MODE) TEST and MODE are the test pins. TEST and MODE must be low while using the LV4904V. Table 2.11 shows the TEST, MODE function settings. Table 2.11 TEST, MODE pin settings TEST, MODE Setting L Setting when using the LV4904V H Inhibited No.A1963-11/25 11 Page

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