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PDF LV5052V Data sheet ( Hoja de datos )
| Número de pieza | LV5052V | |
| Descripción | DC-DC Converter Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LV5052V (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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Ordering number : ENA1394
LV5052V
Bi-CMOS IC
DC/DC Converter Controller
Built-in 2-channels
http://onsemi.com
Overview
The LV5052V is a high efficiency DC/DC converter controller with 2-channels IC adopting a synchronous rectifying
system. Incorporating numerous functions on a single chip with easy external setting, it can be used for a wide variety
of applications. This device is optimal for use in internal power supply systems which are used in electronic devices,
LCD-TVs, DVD recorders, etc.
Functions
• Step-down DC/DC converter controller with 2-channel
• Built-in input UVLO circuit, Over current detection function, soft-start/soft-stop function and Start-up delay circuit
• Built-in output voltage monitor function (Under voltage protection with power good and timer latch)
• 180 degree interleaving operation during 1-phase to 2-phase
• Synchronized operation is possible (Master-slave operation is possible when using plural devices)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
Output peak current
Allowable power dissipation
VIN
IOUT
Pd max
Mounted on a specified board *1
18
±1.0
1.0
V
A
W
Operating temperature
Topr
-20 to 85
°C
Storage temperature
Tstg
-55 to +150
°C
Allowable terminal voltage *2
1 HDRV1,2, CBOOT1,2
25 V
2 Between HDRV1,2, CBOOT1,2
and SW1,2
6.5 V
3 VIN, ILIM1,2, RSNS1,2, SW1,2,
PGOOD1,2
18 V
4 VLIN5, VDD, LDRV1,2
5 COMP1,2, FB1,2, SS1,2,
UV_DELAY,TD1,2, CT, CLKO
6.5
VLIN5+0.3
V
V
*1: Specified board: 114.3mm × 76.1mm ×1.6mm, glass epoxy board.
*2: The Allowable Terminal Voltage, the SGND+PGND pin becomes a standard except for No.2 of the allowable terminal voltage about No.2 of the allowable
terminal voltage, the SW pin becomes a standard.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
August, 2013
12809 MS 20081209-S00004 No.A1394-1/9
1 page  
Block Diagram
LV5052V
COMP1
BG
reference
Voltage
and
BG
current
generator
IREF
Current
bias
Vref
0.84V
VIN
9.0V
/8.0V
VLIN5
4.5V
/4.0V
POR
Vref
VIN
5V REG
(always ON)
VLIN5 5.3V
ILIM
Comp
Internal Bias
Typ 85μA
ILIM1
CH1
output
FB1
0.82Vref
1.18Vref
SS1
3.5μA
Error Amp
UV1
OV1
Vref
1.6V
SD
PWM comp
PWM logic
SKIP control
SS1EN
D
Corrective
ramp
SD
SENSE
Amp
Shifter
& latch
RQ
SQ
Shoot through
protection
sequencer
TD1
COMP2
3.5μA
POR
2.6V
0 deg
CONT1
Active
discharge
Rdson = 15Ω
ILIM
Comp
VIN
RSNS1
CBOOT1
HDRV1
SW1
VDD
LDRV1
Typ 85μA
ILIM2
CH2
output
FB2
0.82Vref
1.18Vref
SS2
3.5μA
Error Amp
UV2
OV2
Vref
1.6V
SD
PWM comp
PWM logic
SKIP control
SS2EN
D
Corrective
ramp
SD
SENSE
Amp
Shifter
& latch
RQ
SQ
Shoot through
protection
sequencer
VIN
TD2
3.5μA
POR
2.6V
180 deg
CONT2
CONT1
CONT2
POR
Active
discharge
Rdson = 15Ω
UV1
SS1EN
UV2
D
SS2EN
D
PGOOD1 PGOOD2
OV1
1μs
9μA
OV2
delay
RQ
0V
SQ
UV
2.6V timeout
UV_DELAY
0 180
deg deg
OSC
300kHz
CT CLKO SGND
Sync. pulse out
5V
0V
RSNS2
CBOOT2
HDRV2
SW2
LDRV2
PGND
Input
Power
Supply
CH1
output
CH2
output
No.A1394-5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LV5052V.PDF ] | |
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