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PDF LE25U40CQE Data sheet ( Hoja de datos )
| Número de pieza | LE25U40CQE | |
| Descripción | 4M-bit (512K x 8) Serial Flash Memory | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA2163
LE25U40CQE
CMOS IC
4M-bit (512K×8)
Serial Flash Memory
http://onsemi.com
Overview
The LE25U40CQE is a SPI bus flash memory device with a 4M bit (512K × 8-bit) configuration that adds a high
performance Dual output and Dual I/O function. It uses a single 2.5V power supply. While making the most of the
features inherent to a serial flash memory device, the LE25U40CQE is housed in an 8-pin ultra-miniature package.
All these features make this device ideally suited to storing program in applications such as portable information
devices, which are required to have increasingly more compact dimensions. The LE25U40CQE also has a small
sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and
conventional EEPROMs cannot handle due to insufficient capacity.
Features
• Read/write operations enabled by single 2.5V power supply: 2.3 to 3.6V supply voltage range
• Operating frequency : 40MHz
• Temperature range
: -40 to 85°C
• Serial interface
: SPI mode 0, mode 3 supported / Dual Output, Dual I/O supported
• Sector size
: 4K bytes/small sector, 64K bytes/sector
• Small sector erase, sector erase, chip erase functions
• Page program function (256 bytes / page)
• Block protect function
• Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ.), 150ms (max.)
Sector erase time
: 80ms (typ.), 250ms (max.)
Chip erase time
: 250ms (typ.), 2.0s (max.)
Page program time : 4.0ms/256 bytes (typ.), 5.0ms/256 bytes (max.)
• Status functions
: Ready/busy information, protect information
• Data retention period : 20 years
• Package
: VSON8T(6.0¯5.0)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
D1912HK 20121120-S00004 No.A2163-1/22
1 page  
LE25U40CQE
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following
(03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 4-a Read"
shows the timing waveforms.
Figure 4-a Read
CS
SCK
SI
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47
8CLK
03h
Add. Add. Add.
SO
1-2. High-speed Read command
High Impedance
N N+1 N+2
DATA DATA DATA
MSB MSB MSB
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8 dummy
bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.
"Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
CS
SCK
SI
SO
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55
8CLK
MSB
0Bh
Add. Add. Add.
High Impedance
X
N N+1 N+2
DATA DATA DATA
MSB MSB MSB
No.A2163-5/22
5 Page 
LE25U40CQE
7. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting
the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19 are "don't
care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends
automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY.
Figure 12 Small Sector Erase
CS
Self-timed
Erase Cycle
tSSE
SCK
SI
SO
Mode3 0 1 2 3 4 5 6 7 8
Mode0
15 16 23 24 31
8CLK
20h / D7h
MSB
Add. Add. Add.
High Impedance
8. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure
13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command
consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h).
Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the
internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal
timer. Erase end can also be detected using status register RDY.
Figure 13 Sector Erase
CS
Self-timed
Erase Cycle
tSE
SCK
SI
SO
Mode3
Mode0
012345678
15 16 23 24 31
8CLK
MSB
D8h
Add. Add. Add.
High Impedance
No.A2163-11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LE25U40CQE.PDF ] | |
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