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PDF NCP81174 Data sheet ( Hoja de datos )
| Número de pieza | NCP81174 | |
| Descripción | 4/3/2-Phase Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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NCP81174
4/3/2-Phase Synchronous
Buck Controller with Power
Saving Mode and PWM VID
Interface
The NCP81174 is a general−purpose up to four−phase synchronous
buck controller. It combines differential voltage sensing, differential
phase current sensing, and PWM VID interface to provide accurate
regulated power for the computer or graphic controllers. It can
receive power saving command (PSI) from processors and operates in
single−phase diode emulation mode to obtain high efficiency in light
load. Dual−edge multiphase PWM modulation ensures a fast transient
response with minimum possible capacitors.
Features
• Output Voltage up to 2.0 V with PWM VID Interface
• Support 1.8 V and 3.3 V VID interface
• Remote Differential Output Voltage Sense
• Differential Current Sense For Each Phase
• 200 kHz − 1000 kHz Switching Frequency
• Power Saving Interface (PSI)
• Power Good Output
• Thermally Compensated Current Monitoring
• Over Current Protection
• Fast Transient Response
• 5 V VCC Shunt Regulator
• Latched OVP and UVP Protections
• QFN−32, 5 x 5 mm, 0.5 mm Pitch Package
• This is a Pb−Free Device
Typical Applications
• GPU and CPU Power
• Graphics Card Applications
• Desktop and Notebook Applications
www.onsemi.com
1 32
QFN32
MW SUFFIX
CASE 488AM
MARKING DIAGRAM
1
NCP81174
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NCP81174MNTXG QFN32 2500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 5
1
Publication Order Number:
NCP81174/D
1 page  
NCP81174
PIN DESCRIPTION
Pin Name
1 VIDBUF
2 VID
3 VR_RDY
4 EN
5 PSI
6 12VMON
7 ROSC
8 ILIM
9 VSP
10 VSN
11 DIFFOUT
12 COMP
13 VFB
14 VDRP
15 VDFB
16 CSSUM
17 CS1N
18 CS1
19 CS2N
20 CS2
21 CS3N
22 CS3
23 CS4N
24 CS4
25 G1
26 G2
27 G3
28 G4
29 DRVON
30 VCC
31 VREF
32 REFIN
33 FLAG
Description
VID PWM pulse output from an internal buffer.
Voltage ID from processor.
Power good indicator.
Chip enable.
Power saving control. Three levels.
12 V input power rail monitor. It is a divided down voltage from the input power rail, should be kept to less
than 4 V at all time.
A resistance from this pin to ground programs the oscillator frequency.
Over current shutdown threshold setting.
Non−inverting input to the internal differential remote sense amplifier.
Inverting input to the internal differential remote sense amplifier.
Output of the differential remote voltage sense amplifier.
Output of the compensation amplifier.
Inverting input of the compensation error amplifier
Voltage signal proportional to the total current.
Current summing amplifier inverting input
Current summing output signal
Inverting input to current sense amplifier, phase 1.
Non−inverting input to current sense amplifier, phase 1.
Inverting input to current sense amplifier, phase 2.
Non−inverting input to current sense amplifier, phase 2.
Inverting input to current sense amplifier, phase 3.
Non−inverting input to current sense amplifier, phase 3.
Inverting input to current sense amplifier, phase 4.
Non−inverting input to current sense amplifier, phase 4.
Phase 1 PWM output, 3 levels.
Phase 2 PWM output, 3 levels.
Phase 3 PWM output, 3 levels.
Phase 4 PWM output, 3 levels.
Gate driver enable.
Power supply for the chip. NCP81174 has a built−in 5 V shunt regulator, allowing it to connect to the external
12 V supply through a resistor. Do not connect a 5 V supply to VCC directly.
2.0 V output reference voltage. A 10 nF ceramic capacitor is recommended to connect this pin to ground.
Reference voltage input for output voltage regulation.
Thermal pad and analog ground, connected to system ground.
www.onsemi.com
5
5 Page 
NCP81174
DETAILED DESCRIPTION
General
The NCP81174, a 4/3/2−phase synchronous buck
controller with PWM VID interface in a QFN−32 package,
provides a compact−footprint power management solution
for new generation computing and graphic processors. It
receives power saving input (PSI) from processors and
operates in 1−phase forced PWM or diode emulation mode
to obtain high efficiency in light−load conditions. It can
either receive PWMVID from the processor to achieve
dynamic voltage control or locally set the reference from an
internal precise 2 V regulator. Operating in high switching
frequency up to 1 MHz allows employing small size
inductor and capacitors. Introduction of dual−edge current
mode multi−phase control results in fast transient response
and good dynamic current balance.
Power Operation Modes
The NCP81174 has three power operation modes
corresponding to PSI levels as shown in Table 1 and 2. The
chip is compatible to different I/O systems. If the upstream
controller has a 3.3 V or higher I/O interface, the
configuration would follow Table 1, the ENABLE signal
needs to be higher than 2.5 V to turn on the chip; If the
upstream controller has a 1.8 V I/O interface, the
configuration would follow Table 2, the ENABLE signal
needs to be higher than 1.1 V only to turn on the chip. The
operation mode can be changed on the fly.
Table 1. POWER SAVING INTERFACE (PSI) CONFIGURATIONS (3.3 V I/O, EN > 2.5 V)
PSI Level
Power Mode
Phase Configuration
High (PSI ≥ 2.4 V) PS0 Full Phase, FCCM
Intermediate (0.8V < PSI < 2.4 V)
PS1
1−Phase, FCCM
Low (PSI ≤ 0.8 V)
PS2 1−Phase, Auto CCM/DCM
Table 2. POWER SAVING INTERFACE (PSI) CONFIGURATIONS (1.8 V I/O, 2.5 V > EN > 1.1 V)
PSI Level
Power Mode
Phase Configuration
High (PSI ≥ 1.4 V) PS0 Full Phase, FCCM
Intermediate (0.8 V < PSI < 1.4 V)
PS1
1−Phase, FCCM
Low (PSI ≤ 0.8 V)
PS2 1−Phase, Auto CCM/DCM
Remote Voltage Sense
A true differential amplifier allows the NCP81174 to
measure Vcore voltage feedback with respect to the Vcore
ground reference point by connecting the Vcore reference
point to VSP, and the Vcore ground reference point to VSN.
This configuration keeps ground potential differences
between the local controller ground and the Vcore ground
reference point from affecting regulation of Vcore between
Vcore and Vcore ground reference points. The remote
sensing amplifier also subtracts the REFIN (DAC) voltage,
thereby producing an unamplified output error voltage at the
DIFFOUT pin. This output also has a 1.3 V bias voltage as
the floating ground to allow both positive and negative error
voltages.
REFIN
VSN
VSP
DIFFOUT
Figure 4. Voltage Remote Sense
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11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NCP81174.PDF ] | |
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