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PDF IN93AA56N Data sheet ( Hoja de datos )
| Número de pieza | IN93AA56N | |
| Descripción | 2K-BIT SERIAL EEPROM | |
| Fabricantes | Integral | |
| Logotipo |  |
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IN93AA56N, IN93AA56D
2K-BIT SERIAL EEPROM WITH MICROWIRE INTEFACE
(compatible to САТ93С56 Catalyst)
DESCRIPTION
The IN93LC56 is a Electric erasable programmable ROM (EEPROM) memory data capac-
ity 2K (256x8 or 128x16) with 3-wire interface.
There are 3 modification of ICs
A: ICs IN93AA56AD/AN are 8 bits registers (256х8) - ORG pin not used
B: ICs IN93AA56BD/BN are 16 bits registers (128х16) - ORG pin not used
C: ICs IN93AA56CN/CD are configured as either registers of 8 bits (ORG pin at GND) or
16 bits (ORG pin at VCC, or not connected). Each register can be written (or read) serially
by using the DI (or DO) pin.
The ICs is purposed for reading, writing & nonvolatile data storage in electronic units with
3-wire interface. ICs can be used in TV-sets, telecom equipment & consumer electronic
devices.
FEATURES
■ 100 year 2K data retention for Ta=25oC;
■ Single power supply source (VСС = 1,8 V – 6,0 V);
■ Build-in voltage multiplier;
■ Serial I/O bus;
■ Autoincrement of word address;
■ Self-timed write cycle with auto-clear;
■ 1,000,000 Program/erase cycles;
■ Power-up internal logic setup;
■ Read cycles quantity are not limited;
■ Low power consumption;
■ Operating temperature range -40 … +85 oC.
N SUFFIX
DIP
8
1 D SUFFIX
8 SOIC
1
PIN FUNCTIONS
Pin
Name
Function
CS Chip Select
CS 01
08 Vcc
SK Clock Input
DI Serial Data Input
SK 02
07 NC
DO
VCC
GND
ORG*
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
Memory Organization pin *
DI 03
DO 04
06 ORG*(NC)
05 GND
NC No Connection
Note
* this pin is present only in IN93AA56CN, IN93AA56CD:
When the ORG pin is connected to VCC, the x16 organization is selected.
When it is connected to ground, the x8 pin is selected.
If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.
Ver.00/13.10.2006
1 IN93AA56-TSe.doc
877568
1 page  
IN93AA56N, IN93AA56D
Instruction Set
Start
Instruction Bit
READ
1
ERASE
1
WRITE
1
Op-
code
10
11
01
EWEN
1 00
Address
x8
x16
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
11XXXXXXX
A7-A0
11XXXXXX
Data
x8 x16
D7-D0
D15-
D0
Comments
Read Address
AN- АО
Clear Address
AN- АО
Write Address
AN- АО
Write Enable
EWDS
1 00 00XXXXXXX 00XXXXXX
Write Disable
ERAL
1 00 10XXXXXXX 10XXXXXX
Clear All
Addresses
WRAL
1
00
01XXXXXXX
01XXXXXX
D7-D0
D15-
D0
Write All
Addresses
Note – Address bits A8 is not used, but must be "1" or "0" for READ, ERASE, WRITE in-
structions
There are 7 instructions 11bit for 128х16 or 12bit for 256x8 memory organization to
execute WRITE, ERASE or READ operation
The format for all instructions sent to the device is a logical "1" start bit, a 2-bits (or 4-bits)
operation code, 8-bit address (128х16)/ 9-bit address (256x8).
High address bit is inessential for decoding and can be any (“1” or “0”)
A 16-bit data field (organization 128х16) or 8-bit data field (organization 256x8) is
additionally required for write operations.
Read Instruction Timing
EWEN/EWDS Instruction Timing
5
Ver.00/13.10.2006
IN93AA56-TSe.doc
877568
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IN93AA56N.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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| IN93AA56BN | EEPROM Integrated circuit | Integral |
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