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PDF IN24AA02 Data sheet ( Hoja de datos )
| Número de pieza | IN24AA02 | |
| Descripción | 2K 1.8V CMOS Serial EEPROMs | |
| Fabricantes | Integral | |
| Logotipo |  |
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TECHNICAL DATA
2K 1.8V CMOS Serial EEPROMs
IN24AA02
DESCRIPTION
IN24AA02 is a 2K-bit Electrically Erasable PROM. The
device is organized as a single block of 256x8 bit
memory with a two-wire serial interface. Low voltage
design permits operation down to 1.8V with standby
and active currents of only 1μA and 3mA respectively.
The IN24AA02 also has a page-write capability for up
to 8 bytes of data.
FEATURES
Single supply with operation down to 1.8V
Two version:
o Version A – pins A0, A1, A2 are using for the
addressing on a single bus system (up to eight
ICs),
o Version B – pins A0, A1, A2 are not using. Only
one IC may be using on a bus.
Low power CMOS technology
Organized as a single block of 256 bytes (256x8)
Two wire serial interface bus, IIC compatible
Schmitt trigger, filtered inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (1.8V) and 400 kHz (2.5-5.5V) compatibility
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
6 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 2,000V
1,000,000 ERASE/WRITE cycles guaranteed
Data retention > 200 years
8-pin DIP, 8-pin SOP
Temperature range -40°C to +85°C (industrial)
Package Types
PIN ASSIGNMENT
PINNING
Name
Function
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock
WP
VCC
AO, A1, A2
Write Protect Input
+1.8V to 5.5V Power Supply
Pins for device address selection
Note: Pins A0, A1 & A2 are not used for IN24AA02B (No internal connections)
INTEGRAL
1 page  
IN24AA02
only the last sixteen will be stored when doing a write operation. When an overwrite
does occur it will replace data in a first in first out fashion.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is
associated with this acknowledge bit.
Note: The IN24AA02 does not generate any acknowledge bits if an internal
programming cycle is in progress
The device that acknowledges, has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the
slave must leave the data line HIGH to enable the master to generate the STOP
condition.
Figure 4. Data Transfer Sequence on the serial bus
BUS CHARACTERISTICS
Slave Address
The IN24AA02 are software-compatible with devices such as 24C01A, 24C02A, 24LC01,
and 24LC02. A single 24AA02 can be used in place of two 24AA01's, for example,
without any modifications to software. The "chip select" portion of the control byte
becomes don't care.
After generating a START condition, the bus master transmits the slave address
consisting of a 4-bit device code (1010) for the IN24AA02, followed by three bits address
selection (In a case of IN24AA02B these three bits can be anyone). The eighth bit of
slave address determines if the master device wants to read or write to the IN24AA02
(see Figure 5).
The IN24AA02 monitors the bus for its corresponding slave address all the time. It
generates an acknowledge bit if the slave address was true and it is not in a
programming mode.
INTEGRAL
5
5 Page 
IN24AA02
A
85
B
14
N SUFFIX PLASTIC DIP
(MS – 001BA)
F
C
-T- SEATING
PLANE
N
GK
D
M
0.25 (0.010) M T
clude mold flash or protrusions.
0.25 mm (0.010) per side.
L
J
H
Symbol Dimensin, mm
min max
A 8.51 10.16
NOT
B 6.10 7.11
ES:
1. Di
C
5.33
m D 0.36 0.56
en
si
F
on G
1.14 1.78
2.54
sH
“A
”,
J
7.62
0° 10°
“B
K 2.92
3.81
”
do
L
7.62 8.26
no M
0.20 0.36
t
in
N
0.38
Maximum mold flash or protrusions
A
85
D SUFFIX SOIC
(MS - 012AA)
H BP
1 G4
C
R x 45
-T-
D
SEATING
K PLANE
J
F
M
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B -
0.25 mm (0.010) per side.
Symb
ol
A
B
C
D
F
G
H
J
K
M
P
R
Dimensin, mm
min max
4.80 5.00
3.80 4.00
1.35 1.75
0.33 0.51
0.40 1.27
1.27
5.72
0° 8°
0.10 0.25
0.19 0.25
5.80 6.20
0.25 0.50
INTEGRAL
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IN24AA02.PDF ] | |
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