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PDF RDA8851AL Data sheet ( Hoja de datos )
| Número de pieza | RDA8851AL | |
| Descripción | GSM/GPRS Single-Chip Terminal | |
| Fabricantes | RDA | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RDA8851AL (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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RDA8851AL Datasheet V1.06
RDA8851AL GSM/GPRS Single-Chip Terminal
FEATURES
●
● External Memory Interface
Integrated 32Mb 1.8V Flash on chip, and also
Supports external SPI Flash
Integrated PSRAM on chip, 16Mb size
Power efficient using retention technology to
avoid floating lines
Flexible IO voltage
●
Connectivity
USB 1.1 Device
2 UART interface
1 SD controller
1 SD/SPI controller
SPI with multiple chip select
I2C controller
General Purpose I/Os
2 GPADC, 10bits, 2 channels
Audio
● GSM/GPRS Modem
2 channels voice ADC, 8kHz, 13 bits/sample
for headset and on-board microphone
GPRS Class 10
Voice DAC, 8kHz, 13 bits/sample for
Quad bands integrated transceiver
receiver
Supports HR, FR, EFR, AMR voice codec
High fidelity Stereo DAC, up to 48kHz, 16
Triple SIM controller with integrated level shifters
bits per sample
Provide a complete GSM/GPRS data path with
Stereo Audio speaker driver
integrated RF transceiver, Saw-Less, only needs
1.5W differential output stereo amplifier for
external PA
loudspeaker, Class K
Stereo analog audio line input
● Multimedia
Support camera interface up to 3Mpix sensors ● Debug
with 8 bit parallel or 1/2/4 data series
Host debug interface allowing non intrusive
interface,Support CSI camera interface
in depth investigation
Support LCD module interface with 8 bit parallel
GDB debugger
interface or SPI series interface
Execution logger and profiling through debug
Support up to 480X640 resolution
port
4-layers blending graphical engine capable of
High level text based debugging using Host
resizing and YUV2RGB conversion
debug or USB
Proprietary 16/32-bit digital signal processing
engine to improve computation performance
● FM
● Power Management
Integrated Broadcast FM tuner which can be
tuned world-wide frequency band
Power On reset control
Internal 32K OSC for standby/ shutoff/ sleep
state
Battery charger (from USB or AC charger)
Integrated all internal voltages from VBAT
●
Bluetooth
Integrated Bluetooth SoC complaint with 2.1
+ EDR standard
Provide all LDOs for external components
● User Interface
APPLICATIONS
8x8 Keypad scanner with multiple key detection,
support ADC serial interface Keypad
Alerter
Light Pulse Generator for blinking LED
Multi-band GSM/GPRS Mobile Handsets, PDAs,
data terminals and Modems: GSM 850, GSM
900, DCS1800, PCS 1900.
Pulse Width Modulator for Keyboard or backlight
control
The high level of integration achieved on
Touch screen interface
RDA8851AL allows for highly featured phone without
LED drivers for LCD and keyboard backlight
increasing the BOM.
Calendar (Real Time Clock) with alarm
RDA Microelectronics Inc. CONFIDENTIAL
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1 page  
RDA8851AL Datasheet V1.06
Figure Index
Figure 1: RDA8851AL Typical Application ...................................................................................................2
Figure A.1 RDA8851AL Integrated IPs & Interfaces ..................................................................................6
Figure A.2: Digital Baseband Diagram .........................................................................................................9
Figure B.1: XCPU Block Diagram ..............................................................................................................15
Figure B.2: Typical transfer operation ........................................................................................................26
Figure B.3: Debug channel block diagram .................................................................................................28
Figure B.4: General Message Format ........................................................................................................32
Figure B.5: Read Return Message Format ................................................................................................32
Figure B.6: Event Message Format ...........................................................................................................32
Figure B.7: Tx Switch STM ........................................................................................................................34
Figure B.8: IrDA SIR Data Format .............................................................................................................34
Figure B.9: YUV 4:2:2 Subsampling ...........................................................................................................47
Figure B.10: SPI Write & Read Timing .......................................................................................................52
Figure B.11: PMU Power ON .....................................................................................................................53
Figure B.12: POR triggered by POWKEY press ........................................................................................54
Figure B.13: Principle schematic for Power-Profiles usage ........................................................................55
Figure B.14: Charging I-V Curve ................................................................................................................57
Figure B.15: PLL Clock Path ......................................................................................................................59
Figure B.16: Audio Analog IP .....................................................................................................................60
Figure B.17: USB PHY FS 1.1 ..................................................................................................................61
Figure B.18: GPADC Timing Diagram .......................................................................................................62
Figure B.19: RF transceiver block digram ..................................................................................................63
Figure B.20: FM Tuner Block Diagram .......................................................................................................65
Figure B.21: Bluetooth Block Diagram .......................................................................................................67
Figure M.1: SCLK Timing Diagram ............................................................................................................87
Figure M.2: SPI Write Timing Diagram .....................................................................................................87
Figure M.3: SPI Read Timing Diagram ......................................................................................................88
Figure O.1: RDA8851AL Ball out diagram ................................................................................................90
RDA Microelectronics Inc. CONFIDENTIAL
5 / 92
5 Page 
RDA8851AL Datasheet V1.06
Multiplexed trace mechanism
Clock input allowing up to 1840kbps baud rate independent from the system clock
Secured protocol with 8 bits CRC (no error correction)
○ Serial Peripheral Interface (SPI)
Master interface with multi-chip selects
16 bytes FIFO
○ I2C Master Peripheral Interface (I2C)
Master interface
○ RF Serial Peripheral Interface (RF SPI) for internal use
1 chip select
Synchronization from TCU
DMA capabilities via Sys IFC
○ General Purpose Input Output (GPIO)
Up to 21 GPIOs
6 GPIOs can generate interruptions
○ General Purpose Output (GPO)
Up to 7 general purpose outputs for external control
○ Keypad
8x8 matrix support with de-bouncing and interrupt generation
Key On input with de-bouncing and interrupt generation
○ Pulse Width Modulation (PWM)
1 PWL, 1 PWT and 1 LPG
○ GOUDA
4 distinct video sources can be blended to produce final output
Region Of Interest (ROI) handling for partial refresh of the LCD screen
Background color (color filled where no layer is defined)
Embedded LCD controller for direct output (LCD commands buffer in dedicated SRAM)
○ SD/MMC Card Controller
can support 2 peripherals
SD Card specification Version 2.0
SDIO Version 1.10
MMC specification Version 3.1
○ Camera Sensor Controller
On the fly cropping and decimation
Supports up to 3M pixel sensor with ISP
Supports any arbitrary size scaling down from 4096x4096
latch RAM FIFO Size 160*16 bit
Support data format: RGB565, YUV422 and compression data
8-bit parallel data interface from camera sensors
○ Sim Card Interface (SCI)
can support 3 SIM cards
T0 protocol for communication
Even parity handled
DMA capabilities via Sys IFC
○ Timers
1 Real Time Clock Timer (Calendar)
1 24 bits general purpose interval Timers at 16384Hz
RDA Microelectronics Inc. CONFIDENTIAL
11 / 92
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