DS2430A Datasheet PDF - Maxim Integrated
| Part Number | DS2430A | |
| Description | 256-Bit 1-Wire EEPROM | |
| Manufacturers | Maxim Integrated | |
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19-5236; Rev 2/12
DS2430A
256-Bit 1-Wire EEPROM
FEATURES
256-bit Electrically Erasable Programmable
Read Only Memory (EEPROM) plus 64-bit
one-time programmable application register
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures
absolute identity because no two parts are alike
Built-in multidrop controller ensures
compatibility with other MicroLAN products
EEPROM organized as one page of 32 bytes
for random access
Reduces control, address, data, and power to a
single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
15.3kbits per second
8-bit family code specifies DS2430A
communication requirements to reader
Presence detector acknowledges when reader
first applies voltage
Low cost TO-92 or 6-pin TSOC and UCSP
surface mount package
Reads and writes over a wide voltage range of
2.8V to 5.25V from -40°C to +85°C
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS2430A+
-40°C to +85°C 3 TO-92
DS2430A+T&R -40°C to +85°C 3 TO-92 (2k pcs)
DS2430AP+
-40°C to +85°C 6 TSOC
DS2430AP+T&R -40°C to +85°C 6 TSOC (4k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
PIN ASSIGNMENT
TO-92
DALLAS
DS2430A
TSOC PACKAGE
16
25
34
TOP VIEW
3.7mm x 4.0mm x 1.5mm
SIDE VIEW
123
12 3
BOTTOM VIEW
NOTE: The leads of TO-92 packages on tape and reel are formed
to approximately 100-mil (2.54mm) spacing. For details see the
Package Information.
PIN DESCRIPTION
TO-92 TSOC
Pin 1 Ground Ground
Pin 2 Data
Data
Pin 3 NC
NC
Pin 4 ––––
NC
Pin 5 ––––
NC
Pin 6 ––––
NC
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DS2430A
MEMORY
The memory of the DS2430A consists of three separate sections, called data memory, application
register, and status register (Figure 5). The data memory and the application register each have its own
intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data
memory can be read and written as often as desired. The application register, however, is one-time
programmable only. Once the application register is programmed, it is automatically write protected. The
status register indicates whether the application register is already locked or whether it is still available
for storing data. As long as the application register is unprogrammed, the status register reads FFh.
Copying data from the register scratchpad to the application register clears the 2 least significant bits of
the status register, yielding an FCh the next time one reads the status register.
DS2430A MEMORY MAP Figure 5
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the different
memory sections of the DS2430A. An example is shown later in this document.
WRITE SCRATCHPAD [0Fh]
After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by
the data to be written to the scratchpad for the data memory. The DS2430A automatically increments the
address after every byte it receives. After having received a data byte for address 1Fh, the address counter
wraps around to 00h for the next byte and writing continues until the master sends a Reset Pulse.
READ SCRATCHPAD [AAh]
This command is used to verify data previously written to the scratchpad before it is copied into the final
storage EEPROM memory. After issuing the Read Scratchpad command, the master must provide the 1-
byte starting address from where data is to be read. The DS2430A automatically increments the address
after every byte read by the master. After the data at address 1Fh has been read, the address counter wraps
around to 00h for the next byte and reading continues until the master sends a Reset Pulse.
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| Information | Total 19 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ DS2430A.PDF Datasheet ] | |
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