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PDF MBR30100CT Data sheet ( Hoja de datos )

Número de pieza MBR30100CT
Descripción 30 AMPERES SCHOTTKY BARRIER RECTIFIERS
Fabricantes E-DA SEMICONDUCTOR 
Logotipo E-DA SEMICONDUCTOR Logotipo



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E-DA SEMICONDUCTOR
RoHS Compliant Product
MBR3040CT~MBR30200CT
30 AMPERES SCHOTTKY BARRIER RECTIFIERS
VOLTAGE 40 to 200 Volts CURRENT 30 Amperes
  Green
FEATURES
• Plastic package has Underwriters Laboratory
Flammability Classification 94V-O.
Flame Retardant Epoxy Molding Compound.
• Metal silicon junction, majority carrier conduction
• Low power loss, high efficiency.
• High current capability
• Guardring for overvlotage protection
• For use in low voltage,high frequency inverters
free wheeling , and polarlity protection applications.
• In compliance with EU RoHS 2002/95/EC directives
.037(0.94)
.022(0.55)
.026(0.66)
.012(0.31)
MECHANICALDATA
• Case: TO-220AB molded plastic
• Terminals: solder plated, solderable per MIL-STD-750, Method 2026
• Polarity: As marked.
• Mounting Position: Any
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
Ratings at 25°C ambient temperature unless otherwise specified. Single phase, half wave, 60 Hz, resistive or inductive load.
For capacitive load, derate current by 20%
PARAMETER
Maximum Recurrent Peak Reverse Voltage
MBR
S YMB OL 3040CT
MBR
3045CT
MBR
3050CT
MBR
MBR
3060CT 3080CT
MBR
3090CT
MBR
30100CT
MBR
MBR
30150CT 30200CT UNITS
VRRM
40
45
50
60
80
90
100
150
200 V
Maximum RMS Voltage
VRMS
28
31.5
35
42
56
63
70
105 140 V
Maximum DC Blocking Voltage
VDC 40 45 50 60 80 90 100 150 200 V
Maximum Average Forward Current (See fig.1)
IF (A V )
Peak Forward Surge Current :8.3ms single half sine-
wave superimposed on rated load(JEDEC method)
IF S M
Maximum Forward Voltage at 15A, per leg
VF
Maxi mum D C Reverse C urrent Tc=25 O C
at Rated DC Blocking Voltage Tc=125OC
IR
Typical Thermal Resistance
RθJ C
Operati ng Juncti on Temperature Range
TJ
0.7 0.75
-50 to + 125
30
275
0.85
0. 5
20
1.4
0. 95
-50 to + 150
A
A
V
mA
OC /
W
OC
Storage Temperature Range
TS TG
-50 to + 150
OC
Notes :
Both Bonding and Chip structure are available.
PAGE . 1

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