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PDF LH28F128SPHTD-PTL12A Data sheet ( Hoja de datos )
| Número de pieza | LH28F128SPHTD-PTL12A | |
| Descripción | Flash Memory | |
| Fabricantes | Sharp | |
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PRELIMINARY PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F128SPHTD-PTL12A
Flash Memory
128M (8M × 16/16M × 8)
(Model No.: LHF12P02)
Spec No.: FM03Z008
Issue Date: December 19, 2003
1 page  
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LHF12P02 Preliminary 2
LH28F128SPHTD-PTL12A
128Mbit (8Mbit×16/16Mbit×8)
Page Mode Flash MEMORY
128-Mbit Density
• Bit Organization ×8/×16
High Performance Page Mode Reads
for Memory Array
• 120/25ns 4-Word/ 8-Byte Page Mode
VCC=2.7V-3.6V Operation
• VCCQ for Input/Output Power Supply Isolation
• Automatic Power Savings Mode reduces ICCR
in Static Mode
OTP (One Time Program) Block
• 4-Word/ 8-Byte Factory-Programmed Area
• 3963-Word/ 7926-Byte User-Programmable Area
High Performance Program with Page Buffer
• 16-Word/ 32-Byte Page Buffer
• Page Buffer Program Time 12.5µs/byte (Typ.)
Operating Temperature -40°C to +85°C
Symmetrically-Blocked Architecture
• One-hundred and twenty-eight
64-KWord/ 128-KByte Blocks
Enhanced Data Protection Features
• Individual Block Lock
• Absolute Protection with VPEN≤VPENLK
• Block Erase, (Page Buffer) Program Lockout during
Power Transitions
Automated Erase/Program Algorithms
• Program Time 210µs (Typ.)
• Block Erase Time 1s (Typ.)
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
56-Lead TSOP (Normal Bend)
CMOS Process (P-type silicon substrate)
ETOXTM* Flash Technology
Not designed or rated as radiation hardened
The product, which is Page Mode Flash memory, is a high density, low cost, nonvolatile read/write storage solution for a
wide range of applications. The product can operate at VCC=2.7V-3.6V and VPEN=2.7V-3.6V
The product supports high performance page mode. It allows code execution directly from Flash, thus eliminating time
consuming wait states.
Fast program capability is provided through the use of high speed Page Buffer Program.
The block locking scheme is available for memory array and this scheme provides maximum flexibility for safe nonvolatile
code and data storage.
OTP (One Time Program) block provides an area to store security code and to protect its code.
* ETOX is a trademark of Intel Corporation.
Rev. 0.05
5 Page 
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LHF12P02 Preliminary 8
Table 3. Identifier Codes Address
Manufacturer Code
Device Code
Block Lock Configuration
Code
Code
Manufacturer Code
Device Code
Block is Unlocked
Block is Locked
Address
[A22-A1] (1)
000000H
000001H
Block
Address
+2
Data
[DQ7-DQ0]
B0H
18H
DQ0 = 0
DQ0 = 1
Notes
2
2
3
3
NOTES:
1. The address A0 and BS don't care.
2. "00H" is presented on DQ15-DQ8 in word mode (BYTE#=VIH : ×16 bit).
3. Block Address = The beginning location of a block address. DQ15-DQ1 are reserved for future implementation.
Rev. 0.05
11 Page | ||
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