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PDF ADuM142D Data sheet ( Hoja de datos )
| Número de pieza | ADuM142D | |
| Descripción | 3.0 kV RMS/3.75 kV RMS Quad Digital Isolators | |
| Fabricantes | Analog Devices | |
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Data Sheet
3.0 kV RMS/3.75 kV RMS
Quad Digital Isolators
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
FEATURES
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition
3000 V rms/3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
CQC certification per GB4943.1-2011
Backward compatibility
ADuM140E1/ADuM141E1/ADuM142E1 pin-compatible
with ADuM1400/ADuM1401/ADuM1402
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, SOIC package
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E1 are quad-channel digital isolators
based on Analog Devices, Inc., iCoupler® technology. Combining
high speed, complementary metal-oxide semiconductor (CMOS)
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices and other
integrated couplers. The maximum propagation delay is 13 ns
with a pulse width distortion of less than 3 ns at 5 V operation.
Channel matching is tight at 3.0 ns maximum.
The ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E data channels are independent and
are available in a variety of configurations with a withstand
voltage rating of 3.0 kV rms or 3.75 kV rms (see the Ordering
Guide). The devices operate with the supply voltage on either side
ranging from 1.8 V to 5 V, providing compatibility with lower
voltage systems as well as enabling voltage translation functionality
across the isolation barrier.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1 ADuM140D/ADuM140E 16 VDD2
GND1 2
VIA 3
ENCODE
DECODE
15 GND2
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VIC 5
ENCODE
DECODE
12 VOC
VID 6
ENCODE
DECODE
11 VOD
DISABLE1/NIC 7
GND1 8
10 NIC/VE2
9 GND2
NOTES
1. NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
2. PIN 7 IS DISABLE1 AND PIN 10 IS NIC FOR THE ADuM140D, AND
PIN 7 IS NIC AND PIN 10 IS VE2 FOR THE ADuM140E.
Figure 1. ADuM140D/ADuM140E Functional Block Diagram
VDD1 1 ADuM141D/ADuM141E 16 VDD2
GND1 2
VIA 3
ENCODE
DECODE
15 GND2
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VIC 5
ENCODE
DECODE
12 VOC
VOD 6
DECODE
ENCODE
11 VID
DISABLE1/VE1 7
GND1 8
10 DISABLE2/VE2
9 GND2
NOTES
1. PIN 7 IS DISABLE1 AND PIN 10 IS DISABLE2 FOR THE ADuM141D,
AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM141E.
Figure 2. ADuM141D/ADuM141E Functional Block Diagram
VDD1 1 ADuM142D/ADuM142E 16 VDD2
GND1 2
VIA 3
ENCODE
DECODE
15 GND2
14 VOA
VIB 4
ENCODE
DECODE
13 VOB
VOC 5
DECODE
ENCODE
12 VIC
VOD 6
DECODE
ENCODE
11 VID
DISABLE1/VE1 7
GND1 8
10 DISABLE2/VE2
9 GND2
NOTES
1. PIN 7 IS DISABLE1 AND PIN 10 IS DISABLE2 FOR THE ADuM142D,
AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM142E.
Figure 3. ADuM142D/ADuM142E Functional Block Diagram
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available, by which the outputs transition to a pre-
determined state when the input power supply is not applied or the
inputs are disabled. The ADuM140E1/ADuM141E1/ADuM142E1
are pin-compatible with the ADuM1400/ADuM1401/ADuM1402.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Other patents are pending.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
VE2 Enable Input Pull-Up Current
DISABLE1 Input Pull-Down Current
Tristate Output Current per Channel
Quiescent Supply Current
ADuM140D/ADuM140E
ADuM141D/ADuM141E
ADuM142D/ADuM142E
Symbol Min Typ Max Unit
PW 6.6
ns
150 Mbps
tPHL, tPLH 4.8
6.8 14
ns
PWD
0.7 3
ns
1.5 ps/°C
tPSK 7.5 ns
tPSKCD
tPSKOD
0.7 3.0
0.7 3.0
580
120
ns
ns
ps p-p
ps rms
VIH 0.7 × VDDx
VIL
V
0.3 × VDDx V
VOH VDDx − 0.1 VDDx
VDDx − 0.4 VDDx − 0.2
VOL 0.0 0.1
0.2 0.4
II
−10
+0.01
+10
IPU −10 −3
IPD 9 15
IOZ
−10
+0.01
+10
V
V
V
V
μA
μA
μA
μA
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2 2.12 mA
2.0 2.68 mA
12.0 19.6 mA
2.0 2.8 mA
1.5 2.36 mA
1.8 2.52 mA
9.8 16.7 mA
5.7 9.7 mA
1.6 2.4 mA
1.6 2.4 mA
7.2 11.2 mA
8.4 11.2 mA
Test Conditions/Comments
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
IOx2 = −20 μA, VIx = VIxH3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 μA, VIx = VIxL4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
VE2 = 0 V
DISABLE1 = VDDx
0 V ≤ VOx ≤ VDDx
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
Rev. B | Page 5 of 27
5 Page 
Data Sheet
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 9. R-16 Narrow Body [SOIC_N] Package
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L (I01)
Minimum External Tracking (Creepage)
L (I02)
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
CTI
Value
3000
4.0
4.0
4.5
25.5
>400
II
Unit
V rms
mm min
mm min
mm min
μm min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 10. RW-16 Wide Body [SOIC_W] Package
Parameter
Symbol
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
L (I01)
Minimum External Tracking (Creepage)
L (I02)
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
CTI
Value
3750
7.8
7.8
8.3
25.5
>400
II
Unit
V rms
mm min
mm min
mm min
μm min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 11.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Ambient Thermal Resistance
R-16 Narrow Body [SOIC_N] Package
RW-16 Wide Body [SOIC_W] Package
Symbol Min Typ Max Unit Test Conditions/Comments
RI-O 1013 Ω
CI-O 2.2 pF f = 1 MHz
CI 4.0 pF
θJA 76 °C/W Thermocouple located at center of package underside
θJA 45 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
Rev. B | Page 11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ADuM142D.PDF ] | |
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