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PDF LTM4641 Data sheet ( Hoja de datos )
| Número de pieza | LTM4641 | |
| Descripción | DC/DC uModule Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
n Wide Operating Input Voltage Range: 4.5V to 38V
n 10A DC Typical, 12A Peak Output Current
n Output Range: 0.6V to 6V
n ±1.5% Maximum Total Output DC Voltage Error
n DifferentialRemoteSenseAmplifierforPOLRegulation
n Internal Temperature, Analog Indicator Output
n Overcurrent Foldback and Overtemperature
Protection
n Current Mode Control/Fast Transient Response
n Parallelable for Higher Output Current
n Selectable Pulse-Skipping Operation
n Soft-Start/Voltage Tracking/Pre-Bias Start-Up
n 15mm × 15mm × 5.01mm BGA Package
n SnPb or RoHS Compliant Finish
Input Protection
n UVLO, Overvoltage Shutdown and Latchoff Thresholds
n N-Channel Overvoltage Power-Interrupt MOSFET Driver
n Surge Stopper Capable with Few External Components
Load Protection
n Robust, Resettable Latchoff Overvoltage Protection
n N-Channel Overvoltage Crowbar Power MOSFET Driver
Applications
n Ruggedized Electronics
n Avionics and Industrial Equipment
LTM4641
38V, 10A DC/DC µModule
Regulator with Advanced
Input and Load Protection
Description
The LTM®4641 is a switch mode step-down DC/DC
µModule® (micromodule) regulator with advanced input
and load protection features. Trip detection thresholds for
the following faults are customizable: input undervoltage,
overtemperature, input overvoltage and output overvolt-
age. Select fault conditions can be set for latchoff or
hysteretic restart response—or disabled. Included in the
package are the switching controller and housekeeping ICs,
power MOSFETs, inductor, overvoltage drivers, biasing
circuitry and supporting components. Operating from input
voltages of 4V to 38V (4.5V start-up), the device supports
output voltages from 0.6V to 6V, set by an external resis-
tor network remote sensing the point-of-load’s voltage.
The LTM4641’s high efficiency design can deliver up to
10A continuous current with a few input and output ca-
pacitors. The regulator’s constant on-time current mode
control architecture enables high step-down ratios and
fast response to transient line and load changes. The
LTM4641 is offered in a 15mm × 15mm × 5.01mm with
SnPb or RoHS compliant terminal finish.
L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 5847554, 6100678, 6304066, 6580258, 6677210, 8163643.
Click to view associated TechClip Videos.
Typical Application
µModule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection
4
VIN
4V TO 38V
4.5V START-UP
+
100µF
50V
MSP*
10µF
50V
×2
VING VINGP VINH
3
MTOP
SW
VINL
VOUT
2
750k
fSET
UVLO
INTVCC
DRVCC
RUN
LTM4641
CROWBAR
MBOT
VOSNS+
VOSNS–
GND
5.49k
5.49k
TRACK/SS
OVPGM
10nF
IOVRETRY OVLO FCB LATCH SGND
5.6M
1
MCB**
VOUT
1V
100µF 10A
×3
LOAD
4641 TA01a
SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR
*MSP: (OPTIONAL) SERIES-PASS OVERVOLTAGE POWER INTERRUPT MOSFET, NXP PSMN014-60LS
**MCB: (OPTIONAL) OUTPUT OVERVOLTAGE CROWBAR MOSFET, NXP PH2625L
For more information www.linear.com/LTM4641
1V LSohaodrtP-rCoitreccutiet datfr3o8mVIMN TOP
SHORT-CIRCUIT APPLIED
VINL, VINH (25V/DIV)
CROWBAR (5V/DIV)
1.1VOUT PEAK
4
3
2
VOUT
(200mV/DIV)
4µs/DIV
TESTED AT WORST-CASE CONDITION: NO LOAD
1
4641 TA01b
4641fe
1
1 page  
LTM4641
E lectrical Characteristics The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications
shown in Figure 45, unless otherwise noted.
are
at
TA
=
25°C
(Note
2).
VIN
=
VINH
=
VINL
=
28V,
per
the
typical
application
SYMBOL
IOUT(PK)
PARAMETER
Output Current Limit
IVINH(IOUT_SHORT)
Control Section
VFB
ITRACK/SS
VFCB
IFCB
tON(MIN)
tOFF(MIN)
VOSNS(DM)
VOSNS(CM)
Power Stage Input Current During
Output Short Circuit
Differential Feedback Voltage from
VOSNS+ to VOSNS–
TRACK/SS Pull-Up Current
FCB Threshold
FCB Pin Current
Minimum On-Time
Minimum Off-Time
Remote Sense Pin-Pair Differential
Mode Input Range
Remote Sense Pin-Pair Common
Mode Input Range
RIN(VOSNS+)
Input Resistance
INTVCC, DRVCC, 1VREF
VINTVCC
Internal VCC Voltage
∆VINTVCC(LOAD)
VINTVCC
INTVCC Load Regulation
VINTVCC(LOWLINE)
DRVCC(UVLO)
IDRVCC
INTVCC Voltage at Low Line
DRVCC Undervoltage Lockout
DRVCC Current
V1VREF(DC)
PGOOD Output
VPGOOD(TH)
1VREF DC Voltage Regulation
Power Good Window, Logic State
Transition Thresholds
VPGOOD(HYST)
VPGOOD(VOL)
tPGOOD(DELAY)
Hysteresis
Logic-Low Output Voltage
PGOOD Logic-Low Blanking Time
CONDITIONS
5.1kΩ Pull-Up from PGOOD to 5V Source, IOUT
Ramped Up Until VOUT Below PGOOD Lower
Threshold, PGOOD Pulls Logic Low
VOUT Electrically Shorted to GND
MIN TYP MAX
24
45
IOUT = 0A
VTRACK/SS = 0V
VFCB = 0.8V
(Note 4)
(Note 4)
Valid Differential VOSNS+ -to- VOSNS– Range
(Use RSET1A = RSET1B ≤ 8.2k)
Valid
Valid
VVOOSSNNSS–+
Common
Common
Mode
Mode
Range
Range
(Use RSET1A = RSET1B ≤ 8.2k)
VOSNS+ to GND
l 591 600 609
–0.45
0.76
l0
–1
0.8
0
43
220
0.84
±1
75
300
2.7
l –0.3
l
3
16318 16400 16482
6V ≤ VIN ≤ 38V, INTVCC Not Connected to DRVCC,
DRVCC = 5.3V
RUN = 0V, INTVCC Not Connected to DRVCC,
DRVCC = 5.3V and:
IIIINNTTVVCCCC
Varied
Varied
from
from
0mA
0mA
to
to
–20mA
–30mA
RVIfNSE=T
4.5V,
Value
RRSeEcTo1mA m= RenSdEeT1dBin=
T0aΩble(~10).6VOUT,
DRVCC Rising
DRVCC Falling
INTVCC Not Connected to DRVCC, DRVCC = 5.3V,
RSET1A, RSET1B and RSET2 Setting VOUT to:
1.8VOUT, RfSET = 2MΩ, 0A ≤ IOUT ≤ 10A
(U6s.e0VROSUETT,1AR=fSERTS=ETO1Bpe≤n8, .02Ak)≤ IOUT ≤ 10A
II11VVRREEFF
=
=
0mA
±1mA
l
l
l
l
l
l
5.1
4.2
3.9
3.2
0.985
0.980
5.3
–0.7
–1
4.3
4.05
3.35
11
20
1.000
1.000
5.4
±2
±3
4.2
3.5
18
27
1.015
1.020
Ramping Differential VOSNS+ – VOSNS– Voltage:
Up, PGOOD Goes Logic Low → High
Up, PGOOD Goes Logic High → Low
Down, PGOOD Goes Logic Low → High
Down, PGOOD Goes Logic High → Low
533 556 579
645 660 675
621 644 667
525 540 555
Differential VOSNS+ – VOSNS– Voltage Returning
8 16 24
IPGOOD = 5mA
l 75 400
Delay Between Differential VOSNS+ – VOSNS–
Voltage Exiting PGOOD Valid Window to PGOOD
Going Logic Low (Note 4)
12
UNITS
A
mA
mV
μA
V
μA
ns
ns
V
V
V
Ω
V
%
%
V
V
V
mA
mA
V
V
mV
mV
mV
mV
mV
mV
μs
For more information www.linear.com/LTM4641
4641fe
5
5 Page 
LTM4641
Pin Functions
CROWBAR (B9): Crowbar Output Pin. Normally logic low,
with moderate pull-down strength to SGND.
When an output overvoltage (OOV) condition is detected,
the LTM4641’s fast OOV comparator pulls CROWBAR logic
high through a series-connected internal diode. If utilizing
LTM4641’s OOV feature, CROWBAR should connect to
the gate of a logic-level N-channel MOSFET configured to
crowbar the module’s output voltage (MCB, in Figure 1).
Furthermore, the LTM4641 latches off its output when
CROWBAR nominally exceeds 1.5V and latches HYST
logic low (see HYST).
If not using the OOV protection features of the LTM4641,
leave CROWBAR electrically open circuit.
OVPGM (B10): Output Overvoltage Threshold Programming
Pin. The voltage on this pin sets the trip threshold for the
inverting input pin of LTM4641’s fast OOV comparator.
When left electrically open circuit, resistors internal to the
LTM4641 nominally bias OVPGM to 666mV (OVPTH)—11%
above the nominal VFB feedback voltage (600mV) that the
control loop strives to present to the noninverting input pin
of LTM4641’s fast OOV comparator. The aforementioned
voltages correspond proportionally to the module’s OOV
inception threshold and VOUT’s nominal voltage of regula-
tion, respectively. Altering the OVPGM voltage provides a
means to adjust the OOV threshold; its DC-bias setpoint
can be tightened with simple connections to external
components (see the Applications Information section).
Trace route lengths and widths to this sensitive analog
node should be minimized. Minimize stray capacitance to
this node unless altering the OOV threshold as described
in the Applications Information section and Appendix F.
LATCH (C5): Latchoff Reset Pin. When a latchoff fault oc-
curs, the LTM4641 turns off its output and latches MHYST
on to indicate a fault condition has occurred (see HYST). To
configure the LTM4641 for latched off response to latchoff
faults, connect LATCH to SGND. As long as LATCH is logic
low, the LTM4641 will not unlatch. Regulation can be re-
sumed by cycling VINL or by toggling LATCH from logic low
to high. It is also permissible to connect LATCH to INTVCC;
this configures the LTM4641 for autonomous restart with
a timeout delay (programmed by CTMR—see TMR).
If no latchoff faults are present when LATCH transitions
from logic low to logic high, the LTM4641 immediately un-
latches. If any latchoff fault is present when LATCH is logic
high, a timeout delay timing requirement is imposed: the
LTM4641 will not unlatch until all latchoff fault-monitoring
pins meet operationally valid states for the full duration
of the timeout delay. If LATCH becomes logic low before
that timeout delay has expired, the LTM4641 remains
latched off and the timeout delay is reset. Unlatching the
LTM4641 can be reattempted by pulling LATCH logic high
at a later time.
The following are latchoff fault conditions:
• CROWBAR activates (see CROWBAR)
• Input latchoff overvoltage fault (see OVLO)
• Latchoff overtemperature fault (when OTBH is logic
low; see TEMP and OTBH)
LATCH is a high impedance input and must not be left elec-
trically open circuit. LATCH can be driven by a μController
in intelligent systems: a reasonable implementation for
unlatching the LTM4641 is to pull LATCH logic high for
the maximum anticipated timeout delay time—after which,
HYST can be observed to indicate whether the LTM4641
has become unlatched.
1VREF (C6): Buffered 1V Reference Output Pin. Minimize
capacitance on this pin, to assure the OVPGM and TEMP
pins are operational in a timely manner at power-up. 1VREF
should never be externally loaded except as explained in
the Applications Information section.
VOUT (C9-C12; D9-D12; E9-E12): Power Output Pins of
the LTM4641 DC/DC Converter Power Stage. All VOUT
pins are electrically connected to each other, internally.
Apply output load between these pins and the GND pins.
It is recommended to place output decoupling capacitance
directly between these pins and the GND pins. Review
Table 9. See the Layout Checklist/Example section of the
Applications Information section.
mVVOOeRSnNBd+Se+(dDitno1t)re:ornVuatOelStNthoSis+tphRienea(µddMbifoafecdrkuelnPetiinrae.llgyTuhwliaistthoprVi.nOIRctBoi–ns)ntreoeccatostemtso-t
point so as to allow the user a way to confirm the integrity
For more information www.linear.com/LTM4641
4641fe
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTM4641.PDF ] | |
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