DataSheet.es    


PDF N25Q256A Data sheet ( Hoja de datos )

Número de pieza N25Q256A
Descripción Micron Serial NOR Flash Memory
Fabricantes MICRON 
Logotipo MICRON Logotipo



Hay una vista previa y un enlace de descarga de N25Q256A (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! N25Q256A Hoja de datos, Descripción, Manual

3V, 256Mb: Multiple I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB Sector Erase
N25Q256A
Features
• SPI-compatible serial bus interface
• Double transfer rate (DTR) mode
• 2.7–3.6V single supply voltage
• 108 MHz (MAX) clock frequency supported for all
protocols in single transfer rate (STR) mode
• 54 MHz (MAX) clock frequency supported for all
protocols in DTR mode
• Dual/quad I/O instruction provides increased
throughput up to 54 MB/s
• Supported protocols
– Extended SPI, dual I/O, and quad I/O
– DTR mode supported on all
• Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Continuous read of entire memory via a single com-
mand
– Fast read
– Quad or dual output fast read
– Quad or dual I/O fast read
• Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
• Software reset
• 3-byte and 4-byte addressability mode supported
• 64-byte, user-lockable, one-time programmable
(OTP) dedicated area
• An additional reset pin is available on the following
devices
– N25Q256A83ESF40x, N25Q256A83E1240x,
N25Q256A83ESFA0F
• Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Full-chip erase
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BA19h)
– Unique ID of 17 read-only bytes including: addi-
tional extended device ID (EDID) to identify de-
vice factory options; customized factory data
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC standard, all RoHS compliant
– V-PDFN-8/8mm x 6mm (also known as SON,
DFPN, MLP, MLF)
– SOP2-16/300mils (also known as SO16W, SO16-
Wide, SOIC-16)
– T-PBGA-24b05/6mm x 8mm (also known as
TBGA24)
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. U 01/15 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




N25Q256A pdf
3V, 256Mb: Multiple I/O Serial Flash Memory
Features
List of Tables
Table 1: Signal Descriptions ........................................................................................................................... 10
Table 2: Sectors[511:0] ................................................................................................................................... 13
Table 3: Data Protection using Device Protocols ............................................................................................. 14
Table 4: Memory Sector Protection Truth Table .............................................................................................. 14
Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 15
Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 15
Table 7: SPI Modes ........................................................................................................................................ 17
Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 19
Table 9: Status Register Bit Definitions ........................................................................................................... 21
Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 22
Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 23
Table 12: Sequence of Bytes During Wrap ....................................................................................................... 24
Table 13: Supported Clock Frequencies – STR ................................................................................................. 24
Table 14: Supported Clock Frequencies – DTR ................................................................................................ 24
Table 15: Extended Address Register Bit Definitions ........................................................................................ 25
Table 16: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 26
Table 17: Flag Status Register Bit Definitions .................................................................................................. 26
Table 18: Command Set ................................................................................................................................. 28
Table 19: Lock Register .................................................................................................................................. 35
Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 38
Table 21: Read ID Data Out ............................................................................................................................ 38
Table 22: Extended Device ID, First Byte ......................................................................................................... 38
Table 23: Serial Flash Discovery Parameter Data Structure .............................................................................. 40
Table 24: Parameter ID .................................................................................................................................. 41
Table 25: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 43
Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address ............................. 45
Table 27: Data/Address Lines for PROGRAM Commands ................................................................................ 53
Table 28: Suspend Parameters ....................................................................................................................... 63
Table 29: Operations Allowed/Disallowed During Device States ...................................................................... 64
Table 30: Reset Command Set ........................................................................................................................ 65
Table 31: OTP Control Byte (Byte 64) .............................................................................................................. 67
Table 32: XIP Confirmation Bit ....................................................................................................................... 71
Table 33: Effects of Running XIP in Different Protocols .................................................................................... 71
Table 34: Power-Up Timing and VWI Threshold ............................................................................................... 74
Table 35: AC RESET Conditions ...................................................................................................................... 75
Table 36: Absolute Ratings ............................................................................................................................. 80
Table 37: Operating Conditions ...................................................................................................................... 80
Table 38: Input/Output Capacitance .............................................................................................................. 80
Table 39: AC Timing Input/Output Conditions ............................................................................................... 81
Table 40: DC Current Characteristics and Operating Conditions ...................................................................... 82
Table 41: DC Voltage Characteristics and Operating Conditions ...................................................................... 82
Table 42: AC Characteristics and Operating Conditions ................................................................................... 83
Table 43: Part Number Information ................................................................................................................ 88
Table 44: Package Details ............................................................................................................................... 89
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. U 01/15 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.

5 Page





N25Q256A arduino
3V, 256Mb: Multiple I/O Serial Flash Memory
Signal Descriptions
Table 1: Signal Descriptions (Continued)
Symbol
HOLD#
W#
VPP
VCC
VSS
DNU
NC
Type
Control
Input
Control
Input
Power
Power
Ground
Description
HOLD: Pauses any serial communications with the device without deselecting the device. DQ1
(output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device
must be selected with S# driven LOW.
HOLD# is used for input/output during the following operations: QUAD OUTPUT FAST READ,
QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED
FAST PROGRAM.
In QIO-SPI, HOLD# acts as an I/O (DQ3 functionality), and the HOLD# functionality is disabled
when the device is selected. When the device is deselected (S# is HIGH) in parts with RESET#
functionality, it is possible to reset the device unless this functionality is not disabled by means
of dedicated registers bits.
The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR.
On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a
DTR operation is recognized.
Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in
extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the
voltage range applied to the signal. If voltage range is low (0V to VCC), the signal acts as a
write protection control input. The memory size protected against PROGRAM or ERASE opera-
tions is locked as specified in the status register block protect bits 3:0.
W# is used as an input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD
INPUT/OUTPUT FAST READ operations and in QIO-SPI.
Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power
supply, as defined in the AC Measurement Conditions table.
During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the addition-
al VPP power supply to speed up internal operations. However, to enable this functionality, it is
necessary to set bit 3 of the VECR to 0.
In this case, VPP is used as an I/O until the end of the operation. After the last input data is shif-
ted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal
operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations
start at standard speed.
The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is
disabled.
Device core power supply: Source voltage.
Ground: Reference for the VCC supply voltage.
Do not use.
No connect.
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. U 01/15 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet N25Q256A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
N25Q256AMicron Serial NOR Flash MemoryMICRON
MICRON

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar