PDF HB56D836SBR Data sheet ( Hoja de datos )

Número de pieza	HB56D836SBR
Descripción	High Density Dynamic RAM Module
Fabricantes	Hitachi Semiconductor
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No Preview Available ! HB56D836BR/SBR Series, HB56D436BR/SBR Series 8,388,608-word × 36-bit High Density Dynamic RAM Module 4,194,304-word × 36-bit High Density Dynamic RAM Module ADE-203-729A (Z) Rev.1.0 Feb. 20, 1997 Description The HB56D836BR/SBR is a 8M × 36 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package and 8 pieces of 4-Mbit DRAM (HM514100) sealed in SOJ package. The HB56D436BR/SBR is a 4M × 36 dynamic RAM module, mounted 8 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package and 4 pieces of 4-Mbit DRAM (HM514100) sealed in SOJ package. An outline of the HB56D836BR/SBR, HB56D436BR/SBR is 72-pin single in-line package. Therefore, the HB56D836BR/SBR, HB56D436BR/SBR make high density mounting possible without surface mount technology. The HB56D836BR/SBR, HB56D436BR/SBR provide common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features • 72-pin single in-line package  Outline: 107.95 mm (Length) × 31.75/25.40 mm (Height) × 9.14 mm (Thickness)  Lead pitch: 1.27 mm • Single 5 V (±5%) supply • High speed  Access time: tRAC = 60/70ns (max) • Low power dissipation  Active mode: 6.41/5.78 W (max) (HB56D836BR/SBR Series) 6.09/5.46 W (max) (HB56D436BR/SBR Series)  Standby mode (TTL): 252 mW (max) (HB56D836BR/SBR Series) (TTL): 126 mW (max) (HB56D436BR/SBR Series) (CMOS): 16.8 mW (max) (L-version) (HB56D836BR/SBR Series) (CMOS): 8.4 mW (max) (L-version) (HB56D436BR/SBR Series) • Fast page mode capability • Refresh period  2048 refresh cycles: 32 ms 128 ms (L-version) 1 page Block Diagram (HB56D836BR/SBR) Datasheet Title RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 CAS1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 RAS2 CAS2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 CAS3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 Note: D0 – D15 : HM5117400 M0 – M7 : HM514100 DQ35 A0 – A10 WE VCC VSS I/O CAS RAS I/O I/O D0 I/O OE I/O CAS RAS I/O I/O D3 I/O OE Din CAS RAS Dout M0 I/O CAS RAS I/O I/O D4 I/O OE I/O CAS RAS I/O I/O D7 I/O OE Din CAS RAS Dout M2 I/O CAS RAS I/O I/O D1 I/O OE I/O CAS RAS I/O I/O D2 I/O OE Din CAS RAS Dout M1 I/O CAS RAS I/O I/O D5 I/O OE I/O CAS RAS I/O I/O D6 I/O OE Din CAS RAS Dout M3 I/O CAS RAS I/O I/O D8 I/O OE I/O CAS RAS I/O I/O D11 I/O OE Din CAS RAS Dout M4 I/O CAS RAS I/O I/O D9 I/O OE I/O CAS RAS I/O I/O D10 I/O OE Din CAS RAS Dout M5 I/O CAS RAS I/O I/O D12 I/O OE I/O CAS RAS I/O I/O D15 I/O OE Din CAS RAS Dout M6 I/O CAS RAS I/O I/O D13 I/O OE I/O CAS RAS I/O I/O D14 I/O OE Din CAS RAS Dout M7 D0 – D15, M0 – M7 D0 – D15, M0 – M7 D0 – D15, M0 – M7 0.22 µF × 14 pcs D0 – D15, M0 – M7 RAS1 RAS3 5 5 Page Datasheet Title AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) 1, 2, *17 Test Conditions • Input rise and fall times: 5 ns • Input timing reference levels: 0.8 V, 2.4 V • Output timing reference levels: 0.4 V, 2.4 V • Output load: 2 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, and Refresh Cycles (Common parameters) Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time CAS delay time from Din Transition time (rise and fall) Refresh period (2,048 cycles) Refresh period (2,048 cycles) (L-version) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t DZC tT t REF t REF 60 ns Min 110 40 10 60 15 0 10 0 15 20 15 15 60 10 0 3 — — 70 ns Max Min — 130 — 50 — 10 10000 70 10000 20 —0 — 10 —0 — 15 45 20 30 15 — 20 — 70 — 10 —0 50 3 32 — 128 — Max Unit — ns — ns — ns 10000 ns 10000 ns — ns — ns — ns — ns 50 ns 35 ns — ns — ns — ns — ns 50 ns 32 ms 128 ms Notes 3 4 5 11 11 Page

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