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PDF HB56D473EJ-7 Data sheet ( Hoja de datos )
| Número de pieza | HB56D473EJ-7 | |
| Descripción | High Density Dynamic RAM Module | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HB56D473EJ Series
4,194,304-word × 72-bit High Density Dynamic RAM Module
ADE-203-725A (Z)
Rev. 1.0
Feb. 27, 1997
Description
The HB56D473EJ belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 4 and 8 Byte processor applications. The
HB56D473EJ is a 4M × 72 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM5117400)
sealed in SOJ package and 8 pieces of 4-Mbit DRAM (HM514100) sealed in SOJ package, 1 pieces of 16-
bit BiCMOS line driver (74ABT16244) sealed in TSSOP package and 1 pieces of 20-bit BiCMOS line
driver (74ABT16827) sealed in TSSOP package. An outline of the HB56D473EJ is 168-pin socket type
package (dual lead out). Therefore, the HB56D473EJ makes high density mounting possible without
surface mount technology. The HB56D473EJ provides common data inputs and outputs. Decoupling
capacitors are mounted on the module board.
Features
• 168-pin socket type package (Dual lead out)
Outline: 133.35 mm (Length) × 25.40 mm (Height) × 9.00 mm (Thickness)
Lead pitch: 1.27 mm
• Single 5 V (±5%) supply
• High speed
Access time: tRAC = 60/70 ns (max)
tCAC = 20/25 ns (max)
• Low power dissipation
Active mode: 12.5/11.3 W (max)
Standby mode (TTL): 588 mW (max)
(CMOS): 462 mW (max)
• Buffered input except RAS and DQ
• 4 byte interleave enabled, dual address input (A0/B0)
• JEDEC standard outline buffered 8-byte DIMM
• Fast page mode capability
• 2,048 refresh cycles: 32 ms
1 page  
Presence Detect Pin Assignment
PDE = Low
Pin name
Pin No.
60 ns
PD1 79
1
PD2 163
1
PD3 80
0
PD4 164
1
PD5 81
0
PD6 165
1
PD7 82
1
PD8 166
1
Note: 1: High level (driver output)
0: Low level (driver output)
70 ns
1
1
0
1
0
0
1
1
HB56D473EJ Series
PDE = High
All
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
5 Page 
Refresh Cycle
Parameter
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
WE setup time (CBR refresh cycle)
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
HB56D473EJ Series
Symbol
t CSR
t CHR
t WRP
t WRH
t RPC
60 ns
Min
15
10
5
10
10
Max
—
—
—
—
—
70 ns
Min
15
10
5
10
10
Max
—
—
—
—
—
Unit Notes
ns
ns
ns
ns
ns
Fast Page Mode Cycle
Parameter
Fast page mode cycle time
Fast page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
Symbol
t PC
t RASP
t CPA
t CPRH
60 ns
Min
40
—
—
40
70 ns
Max Min
— 45
100000 —
40 —
— 45
Max Unit
— ns
100000 ns
45 ns
— ns
Notes
16
9, 17
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet HB56D473EJ-7.PDF ] | |
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