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PDF FSTUD32211 Data sheet ( Hoja de datos )
| Número de pieza | FSTUD32211 | |
| Descripción | 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) | |
| Fabricantes | Fairchild Semiconductor | |
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Preliminary
February 2001
Revised August 2001
FSTUD32211
40/48-Bit Bus Switch with -2V Undershoot Protection
and Level Shifting (Preliminary)
General Description
The Fairchild Switch FSTUD32211 provides up to 48-bits
of high-speed CMOS TTL-compatible bus switching. The
low On Resistance of the switch allows inputs to be con-
nected to outputs without adding propagation delay or gen-
erating additional ground bounce noise. A diode to VCC has
been integrated into the circuit to allow for level shifting
between 5V inputs and 3.3V outputs.
The device can be organized as four 12-bit, two 24-bit, or
one 48-bit bus switch. When routed as a 40-bit bus switch,
the device can be organized as four 10-bit, two 20-bit or
one 40-bit bus switch. When OE1 is LOW, the switch is ON
and Port 1A is connected to Port 1B. When OE2 is LOW,
the switch is ON and Port 2A is connected to Port 2B.
When OE3 is LOW, the switch is ON and Port 3A is con-
nected to Port 3B. When OE4 is LOW, the switch is ON and
Port 4A is connected to Port 4B. When OE1, OE2, OE3, or
OE4 are HIGH, a high impedance state exists between the
A and B Ports. The A and B Ports are protected against
undershoot to support an extended range to 2.0V below
ground. Fairchild’s integrated Undershoot Hardened Circuit
(UHC) senses undershoot at the I/O’s, and responds by
preventing voltage differentials from developing and turn-
ing on the switch.
Features
s Undershoot protected to −2V (A and B Ports)
s Voltage level shifting
s 4Ω switch connection between two ports
s Minimal propagation delay through the switch
s Low lCC
s Zero bounce in flow-through mode
s Control inputs compatible with TTL level
s See Applications Notes AN-5008 and AN-5021 for UHC
details
s Packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number Package Number
Package Description
FSTUD32211GX
(Note 1)
BGA114A
(Preliminary)
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Note 1: BGA package available in Tape and Reel only.
© 2001 Fairchild Semiconductor Corporation DS500537
www.fairchildsemi.com
1 page  
Preliminary
AC Electrical Characteristics
TA = −40 °C to +85 °C,
Symbol
Parameter
CL = 50pF, RU = RD = 500Ω
VCC = 4.5 – 5.5V
Units
Conditions
Figure
Number
Min Max
tPHL, tPLH
Propagation Delay Bus to Bus (Note 8)
0.25 ns VI = OPEN
Figures
2, 3
tPZH, tPZL
Output Enable Time
1.5
10.0
ns VI = 7V for tPZL
Figures
VI = OPEN for tPZH
2, 3
tPHZ, tPLZ
Output Disable Time
1.5 9.0 ns VI = 7V for tPLZ
Figures
VI = OPEN for tPHZ
2, 3
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 9)
Symbol
Parameter
Typ
CIN Control Pin Input Capacitance
3
CI/O Input/Output Capacitance
6
Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
Max
Units
pF
pF
Conditions
VCC = 5.0V
VCC, OE = 5.0V
Undershoot Characteristic (Note 10)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VOUTU
Output Voltage During Undershoot
2.5
VOH - 0.3
V Figure 1
Note 10: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage
undershoot event.
FIGURE 1.
Device Test Conditions
Parameter
VIN
R1 = R2
VTRI
VCC
Value
see Waveforms
100K
11.0
5.5
Units
V
Ω
V
V
Transient
Input Voltage (VIN) Waveform
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet FSTUD32211.PDF ] | |
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