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PDF FSTD32211 Data sheet ( Hoja de datos )
| Número de pieza | FSTD32211 | |
| Descripción | 40/48-Bit Bus Switch with Level Shifting | |
| Fabricantes | Fairchild Semiconductor | |
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September 2001
Revised July 2002
FSTD32211
40/48-Bit Bus Switch with Level Shifting
General Description
The Fairchild Switch FSTD32211 provides up to 48-bits of
high-speed CMOS TTL-compatible bus switching. The low
on resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. A diode to VCC has been
integrated into the circuit to allow for level shifting between
5V inputs and 3.3V outputs.
The device can be organized as four 12-bit, two 24-bit, or
one 48-bit bus switch. When routed as a 40-bit bus switch,
the device can be organized as four 10-bit, two 20-bit or
one 40-bit bus switch. When OE1 is LOW, the switch is ON
and Port 1A is connected to Port 1B. When OE2 is LOW,
the switch is ON and Port 2A is connected to Port 2B.
When OE3 is LOW, the switch is ON and Port 3A is con-
nected to Port 3B. When OE4 is LOW, the switch is ON and
Port 4A is connected to Port 4B. When OE1, OE2, OE3, or
OE4 are HIGH, a high impedance state exists between the
A and B Ports.
Features
I 4Ω switch connection between two ports
I Voltage level shifting
I Minimal propagation delay through the switch
I Low lCC
I Zero bounce in flow-through mode
I Control inputs compatible with TTL level
I Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number Package Number
Package Description
FSTD32211G
(Note 1)(Note 2)
BGA114A
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 2002 Fairchild Semiconductor Corporation DS500378
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
TA = −40 °C to +85 °C,
Symbol
Parameter
CL = 50pF, RU = RD = 500Ω
VCC = 4.5 – 5.5V
Units
Conditions
Figure
Number
Min Max
tPHL, tPLH
Propagation Delay Bus to Bus (Note 9)
0.25
ns VI = OPEN
Figures
1, 2
tPZH, tPZL
Output Enable Time
1.5
10.0
ns VI = 7V for tPZL
VI = OPEN for tPZH
Figures
1, 2
tPHZ, tPLZ
Output Disable Time
1.5 9.0 ns VI = 7V for tPLZ
VI = OPEN for tPHZ
Figures
1, 2
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 10)
Symbol
Parameter
Typ
CIN Control Pin Input Capacitance
3
CI/O Input/Output Capacitance
6
Note 10: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
Max
Units
pF
pF
Conditions
VCC = 5.0V
VCC, OE = 5.0V
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
5
www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet FSTD32211.PDF ] | |
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