DS1339 Datasheet PDF - Maxim Integrated
| Part Number | DS1339 | |
| Description | I2C Serial Real-Time Clock | |
| Manufacturers | Maxim Integrated | |
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GENERAL DESCRIPTION
The DS1339 serial real-time clock (RTC) is a low-
power clock/date device with two programmable time-
of-day alarms and a programmable square-wave
output. Address and data are transferred serially
through an I2C bus. The clock/date provides seconds,
minutes, hours, day, date, month, and year
information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1339 has a built-in power-
sense circuit that detects power failures and
automatically switches to the backup supply,
maintaining time, date, and alarm operation.
APPLICATIONS
Handhelds (GPS, POS Terminals)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printers, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Routers, Switches, Servers)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
Pin Configurations appear at end of data sheet.
DS1339
I2C Serial Real-Time Clock
BENEFITS AND FEATURES
Completely Manages All Timekeeping
Functions
o Real-Time Clock Counts Seconds,
Minutes, Hours, Date of the Month,
Month, Day of the Week, and Year
with Leap-Year Compensation Valid
Up to 2100
o Two Time-of-Day Alarms
o Programmable Square-Wave Output
o Oscillator Stop Flag
Interfaces to Most Microcontrollers
o I2C Serial Interface
Low-Power Operation Extends Battery
Backup Run Time
o Automatic Power-Fail Detect and
Switch Circuitry
o Trickle-Charge Capability
Underwriters Laboratories® (UL)
Recognized
Surface-Mount Package with an
Integrated Crystal (DS1339C Saves
Additional Space and Simplifies Design
ORDERING INFORMATION
PART
DS1339C-2#
DS1339C-3#
DS1339C-33#
DS1339U-2+
DS1339U-3+
DS1339U-33+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VOLTAGE (V)
2.0
3.0
3.3
2.0
3.0
3.3
PIN-PACKAGE
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
8 µSOP
8 µSOP
8 µSOP
TOP MARK†
DS1339C-2
DS1339C-3
DS1339C-33
1339 rr-2
1339 rr-3
1339 rr-33
+Denotes a lead(Pb)-free/RoHS-compliant package.
#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. The lead finish is JESD97 category
e3, and is compatible with both lead-based and lead-free soldering processes.
†A “+” anywhere on the top mark indicates a lead(Pb)-free device. A “#” denotes a RoHS-compliant device. rr = second line, revision code
1 of 20
19-5770; Rev 3/15
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DS1339 I2C Serial Real-Time Clock
POWER-UP/DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 2, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
Recovery at Power-Up
tREC (Note 16)
VCC Fall Time; VPF(MAX) to VPF(MIN)
tVCCF
VCC Rise Time; VPF(MIN) to VPF(MAX)
tVCCR
MIN TYP MAX UNITS
2 ms
300 µs
0 µs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA and SQW/INT.
ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled.
Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC, trickle charger disabled.
VCC must be less than 3.63V if the 250Ω resistor is selected.
Using recommended crystal on X1 and X2.
Guaranteed by design; not production tested.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line
is released.
CB—total capacitance of one bus line in pF.
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤
VCC ≤ VCCMAX and 1.3V ≤ VBACKUP ≤ 3.7V.
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
Figure 1. Power-Up/Down Timing
VPF(MVACXC)
VPF(MIN)
tVCCF
INPUTS
RECOGNIZED
DON'T CARE
tVCCR
tREC
RECOGNIZED
OUTPUTS
VALID
HIGH-Z
VALID
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