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PDF 12864-05 Data sheet ( Hoja de datos )
| Número de pieza | 12864-05 | |
| Descripción | 128 x 64 Dot Graphic LCD Assembly | |
| Fabricantes | PACIFIC DISPLAY DEVICES | |
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PACIFIC DISPLAY DEVICES
LCD Component Data Sheet
Model Number: 12864-05
128 x 64 Dot
Graphic LCD Assembly
With NT7108 Graphics Controller
LED & EL Panel Backlight
CONTENTS
1. GENERAL INFORMATION
1.1 Product Overview
1.2 Part Options and Numbering System
1.3 Absolute Maximum Ratings
1.4 Circuit Block Diagram
1.5 Mechanical Characteristics
1.6 Input Signal Function
1.7 LCM Power, Contrast Control and Bias
1.8 LCD Dimensions
2. ELECTRICAL / OPTICAL CHARACTERISTICS
2.1 DC Electrical Characteristics
2.2 AC Electrical Characteristics
2.3 Optical Characteristics
2.4 LED Backlight Characteristics
2.5 EL Panel Backlight Characteristics
3. LCD CONTROLLER CHARACTERISTICS (NT7107 / NT7108)
3.1 LCD Controller Display & Control Functions
3.2 LCD Controller Character Code map
4. RELIABILITY
5. PRECAUTIONS FOR USING LCD MODULES
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139 Avenida Victoria – Suite 100 – San Clemente, CA – 92672
Tel: 949-361-8957 – Fax: 949-361-9158 – Web: www.pacificdisplay.com
1 page  
SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY MODULE
1.8 LCM Dimensions
MODEL NO: 12864-05
PACIFIC DISPLAY DEVICES
01.01.2011
5
5 Page 
SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY MODULE
MODEL NO: 12864-05
3. LCD CONTROLLER CHARACTERISTICS (NT7107 / NT7108)
3.1 LCD Controller Display and Control Functions
■ I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1 or CS2 is in active mode,
input or output of data and instruction do not execute. Therefore internal state is not change. But RSTB can operate
regardless of CS1 and CS2.
■ Input Register
Input register is provided to interface with MPU which is different operating frequency. Input register stores the
data temporarily before writing it into display data RAM.
When CS1 or CS2 is in the active mode, R/W and RS select the input register. The data from MPU is written into
input register and then write it into display data RAM. Data is latched when falling of the E signal and written
automatically into the display data RAM by internal operation.
■ Output Register
Output register stores the data temporarily from display data RAM when CS1 or CS2 is in active mode and R/W
and RS = H. Stored data in display data RAM is latched in output register. When CS1 or CS2 is in active mode and R/W =
H, RS = L, status data (busy check) can be read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in
display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the
data in display data RAM, it needs dummy read. But status read does not need dummy read.
RS R/W
Function
0 0 Instruction
1 Status read (busy check)
1 0 Data write (from input register to display data RAM)
1 Data read (from display data RAM to output register)
■ Reset
System reset can be initialized by setting RST terminal at low level when turning power on, receiving instruction
from MPU. When RST becomes low, following procedure is occurred.
1. Display off
2. Display start line register become set by 0. ( Z-address 0 )
While RST is low level, no instruction except status read can be accepted. Reset status appears at DB4. After DB4
is low, any instruction can be accepted.
The Conditions of power supply at initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item
Reset time
Rise time
Symbol
tRST
tr
VDD
RST
Min.
1.0
---
4.5V
Typ.
---
---
tRST
tr
0.7VDD
0.3VDD
Max.
---
200
Unit
us
ns
PACIFIC DISPLAY DEVICES
01.01.2011
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 12864-05.PDF ] | |
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