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PDF TDA9885 Data sheet ( Hoja de datos )
| Número de pieza | TDA9885 | |
| Descripción | I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA9885; TDA9886
I2C-bus controlled single and
multistandard alignment-free
IF-PLL demodulators
Product specification
Supersedes data of 2002 Mar 05
2003 Oct 02
1 page  
Philips Semiconductors
I2C-bus controlled single and multistandard
alignment-free IF-PLL demodulators
Product specification
TDA9885; TDA9886
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Audio part
Vo(AF)(rms)
THD
BAF(−3dB)
S/NW(AF)
αAM(sup)
PSRRAUD
Vo(intc)(rms)
AF output voltage (RMS value)
total harmonic distortion of audio
signal
−3 dB AF bandwidth
weighted signal-to-noise ratio of
audio signal
AM suppression of
FM demodulator
power supply ripple rejection on
pin AUD
IF intercarrier output level
(RMS value)
27 kHz FM deviation;
50 µs de-emphasis
FM: 27 kHz FM deviation;
50 µs de-emphasis
AM: m = 54 %
without de-emphasis;
dependent on FM-PLL filter
FM: 27 kHz FM deviation;
50 µs de-emphasis;
vision carrier unmodulated
AM: m = 54 %
50 µs de-emphasis;
AM: f = 1 kHz and
m = 54 %; referenced to
27 kHz FM deviation
fripple = 70 Hz; see Fig.6
for AM
for FM
QSS mode; SC1; SC2 off
L standard;
without modulation
intercarrier mode;
PC/SC1 = 20 dB; SC2 off;
note 6
430
−
−
80
52
45
40
20
14
90
90
−
540 650 mV
0.15 0.50 %
0.5 1.0
100 −
%
kHz
56 −
dB
50 −
46 −
dB
dB
26 −
dB
20 −
dB
140 180 mV
140 180 mV
75 −
mV
Reference frequency
fref
Vref(rms)
reference signal frequency
reference signal voltage
(RMS value)
note 7
−
operation as input terminal 80
4
−
− MHz
400 mV
Notes
1. Values of video and sound parameters can be decreased at VP = 4.5 V.
2. For applications without I2C-bus, the time constant (R × C) at the supply must be >1.2 µs (e.g. 1 Ω and 2.2 µF).
3. Condition: luminance range (5 steps) from 0 % to 100 %.
4. AC load: CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on the TV standard) are attenuated
by the integrated sound carrier traps (see Figs 13 to 18; H (s) is the absolute value of transfer function).
5. S/NW is the ratio of the black-to-white amplitude to the black level noise voltage (RMS value measured on pin CVBS).
B = 5 MHz weighted in accordance with “CCIR 567”.
2003 Oct 02
5
5 Page 
Philips Semiconductors
I2C-bus controlled single and multistandard
alignment-free IF-PLL demodulators
Product specification
TDA9885; TDA9886
8.5 VCO and divider
The VCO of the VIF-FPLL operates as an integrated low
radiation relaxation oscillator at double the picture carrier
frequency. The control voltage, required to tune the VCO
to double the picture carrier frequency, is generated at the
loop filter by the frequency phase detector. The possible
frequency range is 50 to 140 MHz (typical value).
The oscillator frequency is divided-by-two to provide two
differential square wave signals with exactly 90 degrees
phase difference, independent of the frequency, for use in
the FPLL detectors, the video demodulator and the
intercarrier mixer.
8.6 AFC and digital acquisition help
Each relaxation oscillator of the VIF-PLL and FM-PLL
demodulator has a wide frequency range. To prevent false
locking of the PLLs and with respect to the catching range,
the digital acquisition help provides an individual control,
until the frequency of the VCO is within the preselected
standard dependent lock-in window of the PLL.
The in-window and out-window control at the FM-PLL is
additionally used to mute the audio stage (if auto mute is
selected via the I2C-bus).
The working principle of the digital acquisition help is as
follows. The PLL VCO output is connected to a down
counter which has a predefined start value (standard
dependent). The VCO frequency clocks the down counter
for a fixed gate time. Thereafter, the down counter stop
value is analysed. In case the stop value is higher (lower)
than the expected value range, the VCO frequency is
lower (higher) than the wanted lock-in window frequency
range. A positive (negative) control current is injected into
the PLL loop filter and consequently the VCO frequency is
increased (decreased) and a new counting cycle starts.
The gate time as well as the control logic of the acquisition
help circuit is dependent on the precision of the reference
signal at pin REF. Operation as a crystal oscillator is
possible as well as connecting this input via a serial
capacitor to an external reference frequency, e.g. the
tuning system oscillator.
The AFC signal is derived from the corresponding down
counter stop value after a counting cycle. The last four bits
are latched and can be read out via the I2C-bus
(see Table 7). Also the digital-to-analog converted value is
given as current at pin AFC.
8.7 Video demodulator and amplifier
The video demodulator is realized by a multiplier which is
designed for low distortion and large bandwidth. The VIF
signal is multiplied with the ‘in phase’ signal of the VIF-PLL
VCO.
The demodulator output signal is fed into the video
preamplifier via a level shift stage with integrated low-pass
filter to achieve carrier harmonics attenuation.
The output signal of the preamplifier is fed to the VIF-AGC
detector (see Section 8.3) and in the sound trap mode also
fed internally to the integrated sound carrier trap
(see Section 8.8). The differential trap output signal is
converted and amplified by the following postamplifier.
The video output level at pin CVBS is 2 V (p-p).
In the bypass mode the output signal of the preamplifier is
fed directly through the postamplifier to pin CVBS. The
output video level is 1.1 V (p-p) for using an external sound
trap with 10 % overall loss.
Noise clipping is provided in both cases.
8.8 Sound carrier trap
The sound carrier trap consists of a reference filter, a
phase detector and the sound trap itself.
A sound carrier reference signal is fed into the reference
low-pass filter and is shifted by nominal 90 degrees. The
phase detector compares the original reference signal with
the signal shifted by the reference filter and produces a
DC voltage by charging or discharging an integrated
capacitor with a current proportional to the phase
difference between both signals, respectively to the
frequency error of the integrated filters. The DC voltage
controls the frequency position of the reference filter and
the sound trap. So the accurate frequency position for the
different standards is set by the sound carrier reference
signal.
The sound trap itself is constructed of three separate traps
to realize sufficient suppression of the first and second
sound carriers.
8.9 SIF amplifier
The SIF amplifier consists of three AC-coupled differential
stages. Gain control is performed by emitter degeneration.
The total gain control range is typically 66 dB. The
differential input impedance is typically 2 kΩ in parallel with
3 pF.
2003 Oct 02
11
11 Page | ||
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| PDF Descargar | [ Datasheet TDA9885.PDF ] | |
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