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PDF A1214 Data sheet ( Hoja de datos )
| Número de pieza | A1214 | |
| Descripción | Continuous-Time Latch | |
| Fabricantes | Allegro | |
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A1210, A1211, A1212, A1213, and A1214
Continuous-Time Latch Family
FEATURES AND BENEFITS
• AEC-Q100 automotive qualified
• Continuous-time operation
□□Fast power-on time
□□Low noise
• Stable operation over full operating temperature range
• Reverse-battery protection
• Solid-state reliability
• Factory-programmed at end-of-line for optimum
performance
• Robust EMC performance
• High ESD rating
• Regulator stability without a bypass capacitor
Packages:
3-Pin SOT23W (suffix LH)
3-Pin SIP (suffix UA)
1
2
Not to scale
3
1
2
3
VCC
DESCRIPTION
The Allegro™ A1210-A1214 Hall-effect latches are next
generation replacements for the popular Allegro 317x and
318x lines of latching switches. The A121x family, produced
with BiCMOS technology, consists of devices that feature fast
power-on time and low-noise operation. Device programming
is performed after packaging, to ensure increased switchpoint
accuracy by eliminating offsets that can be induced by package
stress. Unique Hall element geometries and low-offset amplifiers
help to minimize noise and to reduce the residual offset voltage
normally caused by deviceovermolding, temperatureexcursions,
and thermal stress.
The A1210-A1214 Hall-effect latches include the following on
a single silicon chip: voltage regulator, Hall-voltage generator,
small-signal amplifier, Schmitt trigger, and NMOS output
transistor. The integrated voltage regulator permits operation
from 3.8 to 24 V. The extensive on-board protection circuitry
makes possible a ±30 V absolute maximum voltage rating
for superior protection in automotive and industrial motor
commutation applications, without adding external components.
All devices in the family are identical except for magnetic
switchpoint levels.
The small geometries of the BiCMOS process allow these
devices to be provided in ultrasmall packages. The package
styles available provide magnetically optimized solutions for
most applications. Package LH is an SOT23W, a miniature low-
profile surface-mount package, while package UAis a three-lead
ultramini SIP for through-hole mounting. Each package is lead
(Pb) free, with 100% matte-tin-plated leadframes.
Regulator
To all subcircuits
Amp
VOUT
A1210-DS, Rev. 13
Gain
Offset
Trim
Control
Functional Block Diagram
GND
1 page  
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions
Package LH, on single layer, single-sided PCB with copper limited to
solder pads
Package LH, on single layer, double-sided PCB with 0.926 in2 copper
area
Package UA on single layer, single-sided PCB with copper limited to
solder pads
Value Units
228 ºC/W
110 ºC/W
165 ºC/W
Power Derating Curve
TJ(max) = 165ºC; ICC = ICC(max)
25
24
23
VCC(max)
22
21
20
19
18
17
16
15
14
13
12
11
Low-K PCB, Package LH
(RθJA = 110 ºC/W)
10
9 Minimum-K PCB, Package UA
8
7
6
(RθJA = 165 ºC/W)
Minimum-K PCB, Package LH
5 (RθJA = 228 ºC/W)
4
3
VCC(min)
2
20 40 60 80 100 120 140 160 180
Power DissipatiToenmvpeerrsatuusreA(ºmCb) ient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
20
(RMθiJnAim=(uR1Lmθ6JoA5-wK=-ºKCP1/PC1W0CB)Bº,C,P/PWaac)ckkaaggee
LH
UA
(RMθiJnAim=u2m2-8KºPCC/WB), Package LH
40 60 80 100 120 140 160 180
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
POWER DERATING
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RθJC, is
relatively small component of RθJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN
(1)
ΔT = PD × RθJA
(2)
TJ = TA + ΔT
(3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RθJA = 140 °C/W, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
ΔT = PD × RθJA = 48 mW × 140 °C/W = 7°C
TJ = TA + ΔT = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RθJA and TA.
Example: Reliability for VCC at TA = 150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
RθJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 7.5 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 7.5 mA = 12.1 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet A1214.PDF ] | |
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