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PDF ICS853052 Data sheet ( Hoja de datos )
| Número de pieza | ICS853052 | |
| Descripción | DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL LVPECL MULTIPLEXER | |
| Fabricantes | IDT | |
| Logotipo |  |
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PRELIMINARY
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ICS853052
GENERAL DESCRIPTION
ICS
The ICS853052 is a Dual LVCMOS / LVTTL-to-
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer and
HiPerClockS™ a member of the HiPerClocks™ family of High
Perfor mance Clocks Solutions from IDT. The
ICS853052 has two selectable single ended clock
inputs. The single ended clock input accepts LVCMOS or LVTTL
input levels and translates them to 2.5V, 3.3V or 5V LVPECL
levels. The small outline 8-pin TSSOP or 8-pin SOIC packages
make this device ideal for applications where space, high
performance and low power are important.
FEATURES
• One differential 2.5V, 3.3V or 5V LVPECL output
• Two selectable LVCMOS/LVTTL clock inputs
• Output frequency: TBD
• Additive phase jitter, RMS: 0.06ps (typical)
• Propagation Delay: 370ps (typical)
• 2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
Da Pulldown
1
Db Pulldown
0
SEL Pulldown
Q
nQ
PIN ASSIGNMENT
nc 1
Da 2
Db 3
SEL 4
8 VCC
7Q
6 nQ
5 VEE
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
1
ICS853052AG REV. B JANUARY 16, 2008
1 page  
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
PRELIMINARY
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
Additive Phase Jitter @ 155.52MHz
-20 (12kHz to 20MHz) = 0.06ps typical
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100 1k
10k 100k 1M 10M 100M
-190
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
5
ICS853052AG REV. B JANUARY 16, 2008
5 Page 
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
RELIABILITY INFORMATION
PRELIMINARY
TABLE 7A. θ VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
101.7°C/W
1
90.5°C/W
2
89.8°C/W
TABLE 7B. θ VS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA
θ by Velocity (Linear Feet per Minute)
JA
0 200
Single-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853052 is: 110
Pin compatible with MC100EP58
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
11
ICS853052AG REV. B JANUARY 16, 2008
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS853052.PDF ] | |
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