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NB6L56 fiches techniques PDF

ON Semiconductor - 2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer

Numéro de référence NB6L56
Description 2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer
Fabricant ON Semiconductor 
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NB6L56 fiche technique
NB6L56
2.5V / 3.3V Dual 2:1
Differential Clock / Data
Multiplexer with LVPECL
Outputs
MultiLevel Inputs w/ Internal Termination
The NB6L56 is a high performance Dual 2to1 Differential Clock
or Data multiplexer. The differential inputs incorporate internal 50 W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L56 to accept various Differential logic level
standards, such as LVPECL, CML or LVDS. Outputs are 800 mV
LVPECL signals. For interface options see Figures 12 15.
The NB6L56 produces minimal Clock or Data jitter operating up to
2.5 GHz or 2.5 Gbps, respectively. As such, the NB6L56 is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The NB6L56 is offered in a low profile 5 mm x 5 mm 32pin QFN
package and is a member of the ECLinPS MAXfamily of high
performance Clock / Data products. Application notes, models, and
support documentation are available at www.onsemi.com.
Features
Maximum Input Data Rate > 2.5 Gbps
Maximum Input Clock Frequency > 2.5 GHz
Jitter
< 1 ps RMS RJ (Data)
< 10 ps PP DJ (Data)
< 0.7 ps RMS Crosstalk induced jitter (CLOCK)
360 ps Max Propagation Delay
180 ps Max Rise and Fall Times
Operating Range:
VCC = 2.5 ± 5% (2.375 V to 2.625 V)
VCC =3.3 ± 10% (3.0 V to 3.6 V)
Internal 50 W Input Termination Resistors
Industrial Temp. Range (40°C to 85°C)
QFN32 Package
These are PbFree Devices
Applications
Clock and Data Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
http://onsemi.com
1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
1
NB6L
56
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
A
B
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
May, 2012 Rev. 0
1
Publication Order Number:
NB6L56/D

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