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NTDV3055L104 fiches techniques PDF

ON Semiconductor - Power MOSFET ( Transistor )

Numéro de référence NTDV3055L104
Description Power MOSFET ( Transistor )
Fabricant ON Semiconductor 
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NTDV3055L104 fiche technique
NTD3055L104,
NTDV3055L104
Power MOSFET
12 A, 60 V, Logic Level N−Channel
DPAK/IPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
Lower RDS(on)
Lower VDS(on)
Tighter VSD Specification
Lower Diode Reverse Recovery Time
Lower Reverse Recovery Stored Charge
AEC Q101 Qualified − NTDV3055L104
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage, Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGS
60
60
"15
"20
Vdc
Vdc
Vdc
ID
ID
IDM
PD
TJ, Tstg
12
10
45
48
0.32
2.1
1.5
−55 to
+175
Adc
Apk
W
W/°C
W
W
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH
IL(pk) = 11 A, VDS = 60 Vdc)
Thermal Resistance, − Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8from case for 10 seconds
EAS 61 mJ
RqJC
RqJA
RqJA
TL
3.13 °C/W
71.4
100
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
http://onsemi.com
V(BR)DSS
60 V
RDS(on) TYP
104 mW
D
ID MAX
12 A
N−Channel
G
S
4
4
12
3
DPAK
CASE 369C
STYLE 2
1
2
3
IPAK
CASE 369D
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
1
Gate
2
Drain
3
Source
12 3
Gate Drain Source
A
55L104
Y
WW
G
= Assembly Location*
= Device Code
= Year
= Work Week
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9
1
Publication Order Number:
NTD3055L104/D

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