NVD5890NL Datasheet PDF - ON Semiconductor
| Part Number | NVD5890NL | |
| Description | Power MOSFET ( Transistor ) | |
| Manufacturers | ON Semiconductor | |
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NVD5890NL
Power MOSFET
40 V, 3.7 mW, 123 A, Single N−Channel
DPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• MSL 1 @ 260°C
• 100% Avalanche Tested
• AEC Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Cur-
rent
3)
(RqJC)
(Notes
1
&
TC = 25°C
TC = 85°C
VDSS
VGS
ID
40
"20
123
95
V
V
A
Power Dissipation
(RqJC) (Note 1)
Continuous Drain Cur-
rent
3)
(RqJA)
(Notes
1,
2,
Steady
State
TC = 25°C
TA = 25°C
TA = 85°C
PD
ID
107 W
24 A
18.5
Power Dissipation
(RqJA) (Notes 1 & 2)
Pulsed Drain Current tp=10ms
Current Limited by Package
(Note 3)
TA = 25°C
TA = 25°C
TA = 25°C
PD
IDM
IDmaxPkg
4.0
400
100
W
A
A
Operating Junction and Storage Temperature
TJ, Tstg
−55 to
175
°C
Source Current (Body Diode)
IS 100 A
Single Pulse Drain−to−Source Avalanche
Energy (VGS = 10 V, L = 0.3 mH, IL(pk) =
46.2 A, RG = 25 W)
EAS 320 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and suty cycle.
http://onsemi.com
V(BR)DSS
40 V
RDS(ON) MAX
3.7 mW @ 10 V
5.5 mW @ 4.5 V
ID MAX
123 A
D
N−Channel
G
S
4
12
3
CASE 369C
DPAK
(Bent Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
2
1 Drain 3
Gate Source
Y = Year
WW = Work Week
5890NL = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. 0
1
Publication Order Number:
NVD5890NL/D
|
| |
 
NVD5890NL
TYPICAL PERFORMANCE CURVES
7000
6000
5000
VGS = 0 V
TJ = 25°C
Ciss
4000
3000
2000
1000
0
0
Crss
Coss
10 20 30
DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
40
10 QT
8
6
4 Qgs
Qgd
2
VDS = 15 V
ID = 50 A
TJ = 25°C
0
0 10 20 30 40 50 60 70 80 90
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source Voltage vs.
Total Charge
1000
VDD = 20 V
ID = 50 A
VGS = 10 V
td(off)
td(on)
100
VGS = 0 V
TJ = 25°C
75
100 tr 50
tf 25
10 0
1 10 100 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
1000
100 10 ms
10
1
0.1
100 ms
VGS ≤ 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1 ms
10 ms
dc
1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
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| Information | Total 7 Pages | |
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