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PDF FDMF3035 Data sheet ( Hoja de datos )
| Número de pieza | FDMF3035 | |
| Descripción | Smart Power Stage (SPS) Module | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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February 2015
FDMF3035 – Smart Power Stage (SPS) Module
Features
Supports PS4 Mode for IMVP-8
Compatible with Intersil IMVP-8 PWM Controller
Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip
Package with Flip Chip Low-Side MOSFET
High Current Handling: 50 A
3-State 5 V PWM Input Gate Driver
Low Shutdown Current IVCC < 3 µA
Diode Emulation for Enhanced Light Load
Efficiency
Fairchild PowerTrench® MOSFETs for Clean
Voltage Waveforms and Reduced Ringing
Fairchild SyncFET™ Technology (Integrated
Schottky Diode) in Low-Side MOSFET
Integrated Bootstrap Schottky Diode
Optimized / Extremely Short Dead-Times
Under-Voltage Lockout (UVLO) on VCC
Optimized for Switching Frequencies up to 1.5 MHz
Operating Ambient Temperature Range:
-40°C to +125°C
Fairchild Green Packaging and RoHS Compliance
Description
The SPS family is Fairchild’s next-generation, fully
optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, high-
frequency, synchronous buck, DC-DC applications. The
FDMF3035 integrates a driver IC with a bootstrap
Schottky diode and two power MOSFETs into a
thermally enhanced, ultra-compact 5 mm x 5 mm
package.
With an integrated approach, the SPS switching power
stage is optimized for driver and MOSFET dynamic
performance, minimized system inductance, and power
MOSFET RDS(ON). The SPS family uses Fairchild's high-
performance PowerTrench® MOSFET technology,
which reduces switch ringing, eliminating the need for a
snubber circuit in most buck converter applications.
A driver IC with reduced dead times and propagation
delays further enhances the performance. The
FDMF3035 supports diode emulation (using FCCM pin)
for improved light-load efficiency. The FDMF3035 also
provides a 3-state 5 V PWM input for compatibility with
a wide range of PWM controllers.
Applications
Notebook, Tablet PC and Ultrabook
Servers and Workstations, V-Core and Non-V-Core
DC-DC Converters
Desktop and All-in-One Computers, V-Core and
Non-V-Core DC-DC Converters
High-Current DC-DC Point-of-Load Converters
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number Current Rating
Package
FDMF3035
50 A
31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package
Top Mark
FDMF3035
© 2015 Fairchild Semiconductor Corporation
FDMF3035 • Rev. 1.0
www.fairchildsemi.com
1 page  
Electrical Characteristics
Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum
values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Basic Operation
ICC_SD
Quiescent Current with PWM
and FCCM Pin Floating (PS4
Mode)
ICC=IVCC + IPVCC, PWM=Floating,
FCCM=Floating (Non-Switching)
3 10 µA
ICC_HIGH
ICC_LOW
VUVLO_RISE
VUVLO_FALL
tD_POR
Quiescent Current with PWM Pin ICC=IVCC + IPVCC, PWM=Floating,
Floating and VFCCM=5 V
FCCM=5 V
Quiescent Current with PWM Pin ICC=IVCC + IPVCC, PWM=Floating,
Floating and VFCCM=0 V
FCCM=0V
UVLO Rising Threshold
VCC Rising
UVLO Falling Threshold
VCC Falling
POR Delay to Enable IC
VCC UVLO Rising to Internal PWM
Enable
80 µA
120 µA
3.4 3.9
2.5 3.0
V
V
15 µs
FCCM Input
IFCCM_HIGH
IFCCM_LOW
VIH_FCCM
VTRI_FCCM
VIL_FCCM
tPS_EXIT
PWM Input
Pull-Up Current
Pull-Down Current
FCCM High Level Input Voltage
FCCM 3-State Window
FCCM Low Level Input Voltage
PS4 Exit Latency
VFCCM=5 V
VFCCM=0 V
VCC=PVCC=5 V
VCC=PVCC=5 V
VCC=PVCC=5 V
VCC=PVCC=5 V
50 µA
-50 µA
3.8 V
2.2 2.8 V
1.0 V
15 µs
IPWM_HIGH Pull-Up Current
VFCCM=5 V
250
IPWM_LOW Pull-Down Current
VFCCM=0 V
-250
VIH_PWM PWM High Level Input Voltage VCC=PVCC=5 V
4.1
VTRI_PWM PWM 3-State Window
VCC=PVCC=5 V
1.6 3.4
VIL_PWM PWM Low Level Input Voltage VCC=PVCC=5 V
0.7
tD_HOLD-OFF 3-State Shut-off Time
VCC=PVCC=5 V, TJ=25°C
100 175 250
PWM Propagation Delays & Dead Times (VIN=12 V, VCC=PVCC=5 V, fSW=1 MHz, IOUT=20 A, TA=25°C)
µA
µA
V
V
V
ns
tPD_PHGLL
tPD_PLGHL
tPD_PHGHH
tPD_TSGHH
tPD_TSGLH
tD_DEADON
PWM HIGH Propagation Delay
PWM LOW Propagation Delay
PWM HIGH Propagation Delay
(FCCM Held LOW)
Exiting 3-State Propagation
Delay
Exiting 3-State Propagation
Delay
LS Off to HS On Adaptive Dead
Time
PWM Going HIGH to GL Going
LOW, VIH_PWM to 90% GL
PWM Going LOW to GH(5) Going
LOW, VIL_PWM to 90% GH
PWM Going HIGH to GH Going
HIGH, VIH_PWM to 10% GH
(FCCM=LOW, IL=0, Assumes DCM)
PWM (from 3-State) Going HIGH to
GH Going HIGH, VIH_PWM to 10% GH
PWM (from 3-State) Going LOW to
GL Going HIGH, VIL_PWM to 10% GL
SW <= -0.2 V with GH <= 10%, PWM
Transition LOW to HIGH
25
15
15
35
35
25
ns
ns
ns
ns
ns
ns
tD_DEADOFF
HS Off to LS On Adaptive Dead
Time
SW <= -0.2 V with GL <= 10%, PWM
Transition HIGH to LOW
20
ns
Note:
5. GH = Gate High, internal gate pin of the high-side MOSFET.
Continued on the following page…
© 2015 Fairchild Semiconductor Corporation
FDMF3035 • Rev. 1.0
5
www.fairchildsemi.com
5 Page 
VIH_PWM
PWM
GL
GH-PHASE
(internal)
90%
10%
90%
10%
VIL_PWM
90%
10%
90%
10%
BOOT-GND
PVCC - VF_DBOOT - 1V
tPD_PHGLL = PWM HI to GL LOW, VIH_PWM to 90% GL
tFALL_GL = 90% GL to 10% GL
tD_DEADON = LS Off to HS On Dead Time, 10% GL to
VBOOT-GND <= PVCC - VF_DBOOT - 1V
tRISE_GH = 10% GH to 90% GH, VBOOT-GND <= PVCC -
VF_DBOOT - 1V to VSW_PEAK
tPD_PLGHL = PWM LOW to GH LOW, VIL_PWM to 90%
GH, tPD_PLGLH - tD_DEADOFF - tFALL_GH
tFALL_GH = 90% GH to 10% GH
tD_DEADOFF = HS Off to LS On Dead Time, VSW <= 0V
to 10% GL
tPD_PLGLH = PWM LOW to GL HI, VIL_PWM to 10% GL
SW
tRISE_GL = 10% GL to 90% GL
tPD_PHGLL tD_DEADON tRISE_GH
tFALL_GL
tPD_PLGHL
tD_DEADOFF
tFALL_GH
tRISE_GL
tPD_PLGLH
Figure 25. PWM Timing Diagram
VIH_PWM(11)
VTRI_HI
VTRI_LO(10)
VIL_PWM
PWM
GH-PHASE
(7)
3-State
Window
(8)
(7)
3-State
Window
(8)
VIH_PWM
VTRI_HI(9)
VTRI_LO
VIL_PWM(12)
GL
Figure 26. PWM Threshold Definition
Notes:
6. The timing diagram in Figure 26 assumes very slow ramp on PWM.
7. Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> tD_HOLD-OFF.
8. VTRI_HI = PWM trip level to enter 3-state on PWM falling edge.
9. VTRI_LO = PWM trip level to enter 3-state on PWM rising edge.
10. VIH_PWM = PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.
11. VIL_PWM = PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.
© 2015 Fairchild Semiconductor Corporation
FDMF3035 • Rev. 1.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet FDMF3035.PDF ] | |
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