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PDF NCV4279A Data sheet ( Hoja de datos )
| Número de pieza | NCV4279A | |
| Descripción | 5.0V Micropower 150mA LDO Linear Regulator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCV4279A
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
The NCV4279A is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 150 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the RADJ lead. The regulator is protected
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
If the application requires pullup resistors at the logic outputs Reset
and Sense Out, the NCV4269A with integrated resistors can be used.
Features
• 5.0 V ± 2.0% Output
• Low 150 mA Quiescent Current
• Active Reset Output Low Down to VQ = 1.0 V
• Adjustable Reset Threshold
• 150 mA Output Current Capability
• Fault Protection
♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
• Early Warning through SI/SO Leads
• Internally Fused Leads in SO−14 Package
• Very Low Dropout Voltage
• Electrical Parameters Guaranteed Over Entire Temperature Range
• These are Pb−Free Devices
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 4
1
8
1
14
1
http://onsemi.com
SO−8
D1 SUFFIX
CASE 751
MARKING
DIAGRAMS
8
4279A5
ALYW
G
1
14
SO−14
D2 SUFFIX
CASE 751A
1
NCV4279A5G
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G = Lead Free Indicators
PIN CONNECTIONS
I1
SI
RADJ
D
SO−8
8Q
SO
RO
GND
1
RADJ
D
GND
GND
GND
GND
RO
14
SI
I
GND
GND
GND
Q
SO
SO−14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Publication Order Number:
NCV4279A/D
1 page  
II
1000 mF
CI
470 nF
VI
VSI
NCV4279A
I
ISI SI
D
GND RO
Q IQ
RADJ1
RADJ
SO
IRADJ
RSO
CQ
22 mF
RRO
VQ
ID Iq VRO VSO
VRADJ
CD
100 nF
VD
RADJ2
Figure 2. Measuring Circuit
VI
VQ
VRT
< tRR
VD
VUD
VLD
VRO
VRO,SAT
td
tRR
dV
dt
+
ID
CD
Power−on−Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Figure 3. Reset Timing Diagram
Overload
at Output
t
t
t
t
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5 Page 
NCV4279A
APPLICATION DESCRIPTION
OUTPUT REGULATOR
The output is controlled by a precision trimmed reference.
The PNP output has drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage VLD
the reset output voltage VRO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for VQ as low as 1.0 V.
RESET ADJUST (RADJ)
The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 20. The resistor divider keeps the voltage
above the VRADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) ń RADJ2
(eq. 1)
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D
provides charge current ID,C (typically 6.5 mA) to the
external delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VDSAT to
the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VD, SAT)]ńID
(eq. 2)
Example:
Using CD = 100 nF.
Use the typical value for VD,SAT = 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.
td + [100 nF (1.8 * 0.1 V)] ń 6.5 mA + 26.2 ms (eq. 3)
VBAT
CI*
CD
IQ
0.1 mF
RADJ
NCV4279A
D SI
RADJ1
RADJ2
RSI1
RRO
RSI2
VDD
CQ**
10 mF
(2.2 mF)
RSO
SO RO
GND
I/O I/O
*CI required if regulator is located far from the power supply filter.
** CQ − minimum cap required for stability is 2.2 mF while higher over/under−shoots may be ex-
pected. Cap must operate at required temperature range.
Figure 20. Application Diagram
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NCV4279A.PDF ] | |
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