|
|
PDF NCV7340 Data sheet ( Hoja de datos )
| Número de pieza | NCV7340 | |
| Descripción | High Speed Low Power CAN Transceiver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NCV7340 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
NCV7340
High Speed Low Power CAN
Transceiver
Description
The NCV7340 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
The NCV7340 is a new addition to the CAN high−speed transceiver
family and is an improved drop−in replacement for the AMIS−42665.
Due to the wide common−mode voltage range of the receiver inputs,
the NCV7340 is able to reach outstanding levels of electromagnetic
susceptibility (EMS). Similarly, extremely low electromagnetic
emission (EME) is achieved by the excellent matching of the output
signals.
Features
• Compatible with the ISO 11898 Standard (ISO 11898−2, ISO
11898−5 and SAE J2284)
• Low Quiescent Current
• High Speed (up to 1 Mbps)
• Ideally Suited for 12 V and 24 V Industrial and Automotive
Applications
• Extremely Low Current Standby Mode with Wakeup via the Bus
• Low EME Common−Mode Choke is No Longer Required
• Voltage Source via VSPLIT Pin for Stabilizing the Recessive Bus
Level (Further EMC Improvement)
• No Disturbance of the Bus Lines with an Un−powered Node
• Transmit Data (TxD) Dominant Time−out Function
• Thermal Protection
• Bus Pins Protected Against Transients in an Automotive
Environment
• Bus and VSPLIT Pins Short−Circuit Proof to Supply Voltage and
Ground
• Logic Level Inputs Compatible with 3.3 V Devices
• Up to 110 Nodes can be Connected to the Same Bus in Function of
Topology
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These are Pb−Free Devices
Typical Applications
• Automotive
• Industrial Networks
http://onsemi.com
8
1
SOIC−8
CASE 751AZ
MARKING
DIAGRAM
8
NV7340−x
FALYW G
G
1
NV7340− = Specific Device Code
x = 3 (NCV7340D13R2G)
= 2 (NCV7340D12R2G)
= 4 (NCV7340D14R2G)
F = Fab Location Code*
*For NCV7340D14R2G only
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN ASSIGNMENT
1
TxD
2
GND
3
VCC
4
RxD
8
STB
7
CANH
6
CANL
5
VSPLIT
NCV7340DxxR2G
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 8
1
Publication Order Number:
NCV7340/D
1 page  
NCV7340
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (tdom(TxD)) defines the
minimum possible bit rate to 40 kbps.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min Max Unit
VCC
VCANH
VCANL
VSPLIT
VTxD
VRxD
VSTB
Vesd
Supply voltage
DC voltage at pin CANH
DC voltage at pin CANL
DC voltage at pin VSPLIT
DC voltage at pin TxD
DC voltage at pin RxD
DC voltage at pin STB
Electrostatic discharge voltage at all pins
0 < VCC < 5.25 V; no time limit
0 < VCC < 5.25 V; no time limit
0 < VCC < 5.25 V; no time limit
Note 1
Note 2
−0.3
−50
−50
−40
−0.3
−0.3
−0.3
−6
−500
+6
+50
+50
+40
6
6
6
6
500
V
V
V
V
V
V
V
kV
V
Electrostatic discharge voltage at CANH and CANL pins
Note 3
−12 12 kV
Vschaff
Latchup
Transient voltage, see Figure 5
Static latchup at all pins
Note 5
Note 4
−150
100
120
V
mA
Tstg Storage temperature
−55 +150 °C
TA Ambient temperature
−40 +125 °C
TJ Maximum junction temperature
−40 +170 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor.
4. Static latchup immunity: Static latchup protection level when tested according to EIA/JESD78.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Verification by external test house.
Table 5. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
RqJA_1
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6)
Free air
RqJA_2
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7)
Free air
6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
Value
125
75
Unit
K/W
K/W
http://onsemi.com
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NCV7340.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NCV7340 | High Speed Low Power CAN Transceiver | ON Semiconductor |
| NCV7341 | High Speed Low Power CAN Transceiver | ON Semiconductor |
| NCV7342 | High Speed Low Power CAN Transceiver | ON Semiconductor |
| NCV7349 | High Speed Low Power CAN Transceiver | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |