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Número de pieza | 74VHC08-Q100 | |
Descripción | Quad 2-input AND gate | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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No Preview Available ! 74VHC08-Q100;
74VHCT08-Q100
Quad 2-input AND gate
Rev. 1 — 20 December 2013
Product data sheet
1. General description
The 74VHC08-Q100; 74VHCT08-Q100 are high-speed Si-gate CMOS devices and are
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard JESD7-A.
The 74VHC08-Q100; 74VHCT08-Q100 provide the quad 2-input AND function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than VCC
Input levels:
The 74VHC08-Q100 operates with CMOS logic levels
The 74VHCT08-Q100 operates with TTL logic levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options
1 page NXP Semiconductors
74VHC08-Q100; 74VHCT08-Q100
Quad 2-input AND gate
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
VCC = 3.3 V 0.3 V
VCC = 5.0 V 0.5 V
9. Static characteristics
74VHC08-Q100
Min Typ Max
2.0 5.0 5.5
0-
5.5
0-
VCC
40 +25 +125
- - 100
- - 20
74VHCT08-Q100
Min Typ Max
4.5 5.0 5.5
0-
5.5
0-
VCC
40 +25 +125
---
- - 20
Unit
V
V
V
C
ns/V
ns/V
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
For type 74VHC08-Q100
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 3.0 V
VCC = 5.5 V
VIL LOW-level VCC = 2.0 V
input voltage VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level VI = VIH or VIL
output voltage IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VOL
LOW-level
VI = VIH or VIL
output voltage IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
II input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
CI input
capacitance
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
1.5 - - 1.5
-
1.5
-V
2.1 - - 2.1
-
2.1
-V
3.85 -
- 3.85
-
3.85
-V
- - 0.5 -
0.5
-
0.5 V
- - 0.9 -
0.9
-
0.9 V
- - 1.65 -
1.65
-
1.65 V
1.9 2.0 -
1.9
2.9 3.0 -
2.9
4.4 4.5 -
4.4
2.58 -
- 2.48
3.94 - - 3.8
-
-
-
-
-
1.9
2.9
4.4
2.4
3.7
-V
-V
-V
-V
-V
- 0 0.1 -
0.1
-
0.1 V
- 0 0.1 -
0.1
-
0.1 V
- 0 0.1 -
0.1
-
0.1 V
- - 0.36 -
0.44
-
0.55 V
- - 0.36 -
0.44
-
0.55 V
- - 0.1 -
1.0
-
2.0 A
- - 2.0 -
20
-
40 A
- 3.0 10
-
10
-
10 pF
74VHC_VHCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 December 2013
© NXP B.V. 2013. All rights reserved.
5 of 15
5 Page NXP Semiconductors
74VHC08-Q100; 74VHCT08-Q100
Quad 2-input AND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
D BA
terminal 1
index area
A
A1
E
c
detail X
terminal 1
index area
L
e
2
1
Eh
14
e1
b
6
vM C AB
wM C
7
e
8
y1 C
C
y
13 9
Dh
0 2.5
5 mm
X
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c D(1) Dh E(1) Eh e e1 L
v
w
y y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1 1.65
2.9 1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1 0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT762-1
---
MO-241
---
ISSUE DATE
02-10-17
03-01-27
Fig 10. Package outline SOT762-1 (DHVQFN14)
74VHC_VHCT08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 December 2013
© NXP B.V. 2013. All rights reserved.
11 of 15
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet 74VHC08-Q100.PDF ] |
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