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PDF TC74VHC273FK Data sheet ( Hoja de datos )
| Número de pieza | TC74VHC273FK | |
| Descripción | OCTAL D-TUPE FLIP-FLOP WITH CLEAR | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC74VHC273F/FW/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC273F,TC74VHC273FW,TC74VHC273FT,TC74VHC273FK
Octal D-Type Flip-Flop with Clear
The TC74VHC273 is an advanced high speed CMOS OCTAL
D-TYPE FLIP FLOP fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Information signals applied to D inputs are transferred to the
Q outputs on the positive going edge of the clock pulse.
When the CLR input is held “L”, the Q outputs are at a low
logic level independent of the other inputs.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: fmax = 165 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Low noise: VOLP = 0.9 V (max)
• Pin and function compatible with 74ALS273
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHC273F
TC74VHC273FW
TC74VHC273FT
TC74VHC273FK
Weight
SOP20-P-300-1.27A
: 0.22 g (typ.)
SOP20-P-300-1.27
: 0.22 g (typ.)
SOL20-P-300-1.27
: 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
VSSOP20-P-0030-0.50 : 0.03 g (typ.)
1 2006-06-01
1 page  
TC74VHC273F/FW/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Symbol
Propagation delay
time
(CK-Q)
tpLH
tpHL
Propagation delay
time
( CLR -Q)
tpHL
Maximum clock
frequency
fmax
Output to output skew
Input capacitance
Power dissipation
capacitance
tosLH
tosHL
CIN
CPD
Test Condition
VCC (V)
3.3 ± 0.3
⎯
5.0 ± 0.5
3.3 ± 0.3
⎯
5.0 ± 0.5
3.3 ± 0.3
⎯
5.0 ± 0.5
3.3 ± 0.3
(Note 1)
5.0 ± 0.5
⎯
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Ta = 25°C
Min Typ. Max
⎯ 8.7 13.6
⎯ 11.2 17.1
⎯ 5.8 9.0
⎯ 7.3 11.0
⎯ 8.9 13.6
⎯ 11.4 17.1
⎯ 5.2 8.5
⎯ 6.7 10.5
75 120 ⎯
50 75 ⎯
120 165
⎯
80 110 ⎯
⎯ ⎯ 1.5
⎯ ⎯ 1.0
⎯ 4 10
(Note 2) ⎯ 31 ⎯
Ta = −40 to
85°C
Min Max
1.0 16.0
1.0 19.5
1.0 10.5
1.0 12.5
1.0 16.0
1.0 19.5
1.0 10.0
1.0 12.0
65 ⎯
45 ⎯
100 ⎯
70 ⎯
⎯ 1.5
⎯ 1.0
⎯ 10
⎯⎯
Unit
ns
ns
MHz
ns
pF
pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per bit)
And the total CPD when n pcs.of flip flop operate can be gained by the following equation:
CPD (total) = 22 + 9·n
Noise Characteristics (input: tr = tf = 3 ns) (Note)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
Minimum high level dynamic input
voltage
Maximum low level dynamic input
voltage
VIHD
VILD
CL = 50 pF
CL = 50 pF
Note: The value in ( ) only applies to JEDEC SOP (FW) devices.
VCC (V)
5.0
5.0
Ta = 25°C
Typ. Max
0.5 0.8
(0.6) (0.9)
−0.5 −0.8
(−0.6) (−0.9)
Unit
V
V
5.0 ⎯ 3.5 V
5.0 ⎯ 1.5 V
5 2006-06-01
5 Page 
Package Dimensions
TC74VHC273F/FW/FT/FK
Weight: 0.03 g (typ.)
11 2006-06-01
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet TC74VHC273FK.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TC74VHC273F | OCTAL D-TUPE FLIP-FLOP WITH CLEAR | Toshiba |
| TC74VHC273FK | OCTAL D-TUPE FLIP-FLOP WITH CLEAR | Toshiba |
| TC74VHC273FS | OCTAL D-TUPE FLIP-FLOP WITH CLEAR | Toshiba |
| TC74VHC273FT | OCTAL D-TUPE FLIP-FLOP WITH CLEAR | Toshiba |
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