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PDF PC3030K Data sheet ( Hoja de datos )
| Número de pieza | PC3030K | |
| Descripción | 1/3.7 inch NTSC/PAL CMOS Image Sensor | |
| Fabricantes | Pixelplus | |
| Logotipo |  |
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Preliminary
Data sheet
1/3.7 inch NTSC/PAL CMOS Image Sensor with
640 X 480 Pixel Array
PC3030K
Rev 0.5
Last update : 27. Apr. 2011
6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,
Suwon-si, Gyeonggi-do, 443-766, Korea
Tel : 82-31-888-5300, FAX : 82-31-888-5398
Copyright ⓒ 2011, Pixelplus Co.,Ltd
ALL RIGHTS RESERVED
1 page  
PRELIMINARY
PC3030K
1/3.7 inch NTSC/PAL CMOS Image Sensor with
640 X 480 Pixel Array
▶ Features
▷ 682 x 504 total pixel array with
RGB bayer color filters and micro-lens.
▷ Power supply :
AVDD : 2.8V, HVDD : 3.3V, CVDD : 2.8V
▷ Output formats :
◆ Composite Output mode :
- CVBS ( NTSC/PAL ),
◆ Digital Output mode :
- max. VGA (640x480) YCbCr422/RGB565/
RGB444. ( progressive, 60 fps @ 54MHz )
- max. VGA (640x480) Bayer
( progressive, 60 fps @ 27MHz )
◆ Analog/Digital Output mode :
- ITU-R. BT656 ( 720x240/288 )
( interlaced, 60 fields @ 27MHz )
- CVBS ( 30 fps @ 27MHz )
▷ Image processing on chip : lens shading,
gamma / defect / color correction,
low pass filter, color interpolation, saturation,
edge enhancement, brightness, contrast,
special effects, auto black level ,
auto white balance, auto exposure control
and back light compensation.
▷ Frame size, window size and position can
be programmed through a 2-wire serial
interface bus.
▷ VGA / QVGA / QQVGA / CIF / QCIF Scaling.
▷ High Image Quality and Ultra low light
perf orm ance.
▷ I2C master include.
▷ Motion detection support
▷ Alarm mode, Privacy mode support
▷ Artificial Intelligence power save mode.
▷ Chip Address Selection PADs
▷ Horizontal / Vertical mirroring.
▷ 50Hz, 60Hz flicker automatic cancellation.
▷ Software Reset.
▷ External Sync (Gen. Lock) support
▷ Off-chip IR-LED control.
▷ Crystal input support.
▷ On chip regulator for DVDD.
▷ CSP/CLCC/PLCC Package type supports
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
STDBY 43
CADD1 44
CADD0 45
LED 46
TE 47
GENI 48
GENO 49
MIRS0 50
MIRS1 51
Effevtive Pixel Array
Notch : Bottom
26 SCL
25 SDA
24 DGND
23 HGND
22 HVDD
21 DVDD
20 SCK
19 MISO
18 MOSI
17 CSB
16 D1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(0,0)
[Fig. 1] PIN Description
Total Pixel Array
682 (H) x 504(V)
Effective Pixel Array
648(H) x 488(V)
Pixel Size
6 um x 6 um
Effective Image Area
3.8 mm x 2.9 mm
( Diagonal :4.86mm)
Optical Format
1/3.7 inch , RGB Bayer filter
Max. Clock frequency
Max. Frame Rate
Dark Signal
54 MHz
- 60fps, 640x480 YCbCr @ 54MHz
- 60fps, 640x480 Bayer @ 27MHz
- 60field, 720x240(288) YCbCr
@ 27MHz
- CVBS 30 fps @ 27MHz
11.0 [mV/sec ] @60℃
Sensitivity
8.0 [V/Lux.sec]
Power Supply
Power Consumption
Operating Temp.
(Fully Functional Temp)
Analog : 2.8V,
HVDD : 3.3V,
CVDD : 2.8V
225.9 mW @Dynamic
416.9 uW @Standby
-40 ~ 105 [℃]
Dynamic Range
64.4 [dB]
SNR
47.2 [dB]
[Table 1] Typical Parameters
Rev 0.6
5/122
CrystalImage & ImagingInnovation
5 Page 
PRELIMINARY
PC3030K
1/3.7 inch NTSC/PAL CMOS Image Sensor with
640 X 480 Pixel Array
▶ Data and Synchronization Timing
1) VGA
[Fig. 6] shows the def ault data sequence of PC3030K. In [Fig. 6] VSYNC/HSYNC/PCLK polarity can
have any combinations possible. Data can be latched at the rising or f alling edge of PCLK. HSYNC can be set
to be active high or active low. The sequence def ault YUV data is [ U,Y, V, Y, …] for common even / odd rows.
The positive width of VSYNC can be programmed by vsyncstartrow and vsyncstoprow (register value)
and given by
VSYNC positive width = vsyncstartrow – vsyncstoprow [line]
The positive width of HSYNC can be programmed by windowx1 / x2( Register Value ) and given by
HSYNC positive width = 2 x (windowx2 - windowx1 + 1 ) [PCLK]
Data sequence of YUV f ormat can change to [U, Y, V, Y], [V, Y, U, Y], [Y, U, Y, V] and [Y, V, Y, U] by
format (register value). Data value can be selected in Invalid or blanking region.
VSYNC
HSYNC
VSYNC period = frameheight + 1 [line]
VSYNC positive width = vsyncstoprow – vsyncstartrow [line]
HSYNC period = 2 x ( framewidth + 1 ) [PCLK]
HSYNC positive width = 2 x (windowx2 – windowx1 +1 ) [PCLK]
HSYNC
X1
PCLK
DATA AB U Y V Y U Y
V Y U Y V Y FF 00
AB U
[Fig. 6] Timing Diagram f or VSYNC, HSYNC, X1, PCLK and Data ( YUV mode : def ault )
Rev 0.6
11/122
CrystalImage & ImagingInnovation
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PC3030K.PDF ] | |
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