NB3N111K Datasheet PDF - ON Semiconductor
| Part Number | NB3N111K | |
| Description | 3.3V Differential 1:10 Fanout Clock Driver | |
| Manufacturers | ON Semiconductor | |
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NB3N111K
3.3V Differential 1:10
Fanout Clock Driver with
HCSL Outputs
Description
The NB3N111K is a differential 1:10 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N111K is designed
with PCI Express HCSL clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL
signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external Vth
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS
receivers when terminated per Figure 11.
The NB3N111K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N111K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequency 100, 133, 166, or 400 MHz
• 220 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair
• 0.1 ps Typical RMS Additive Phase Jitter
• LVDS Output Levels Optional with Interface Termination
• Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
• Typical HCSL Output Levels (700 mV Peak−to−Peak)
• LVDS Output Levels with Interface Termination
• These are Pb−Free Devices
Applications
• Clock Distribution
• PCIe I, II, III
• Networking
• High End Computing
• Routers
End Products
• Servers
• FBDIMM Memory Card
© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 5
1
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1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
1
NB3N
111K
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
CLK
CLK
VTCLK
VCC
GND
IREF
RREF
Q0
Q0
Q1
Q1
Q8
Q8
Q9
Q9
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Publication Order Number:
NB3N111K/D
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NB3N111K
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +85°C (Note 6)
Symbol
Characteristic
Min Typ Max Unit
VOUTPP
tPLH,
tPHL
DtPLH,
DtPHL
tSKEW
Output Voltage Amplitude (@ VINPPmin) fin ≤ 400 MHz
Propagation Delay (See Figure 3a)
Propagation Delay Variation Per Each Diff Pair
(Note 7) (See Figure 3a)
Duty Cycle Skew (Note 8)
Within −Device Skew
Device to Device Skew (Note 9)
CLK/CLK to Qx/Qx 550
725 1000
800 1100
mV
ps
CLK/CLK to Qx/Qx
ps
100
20 ps
100
150
tJITq
VINPP
Additive Integrated Phase Jitter at Fc = 100 MHz (Note 10)
Input Voltage Swing/Sensitivity
(Differential Configuration)
0.1 ps
0.150
VCC −
0.85
V
VCROSS
DVCROSS
tr , tf
Absolute Crossing Magnitude Voltage (See Figure 3b)
Variation in Magnitude of VCROSS (See Figure 3b)
Absolute Magnitude in Output Risetime and Falltime (from 175 mV to 525 mV)
(See Figure 3b)
250
Qx, Qx 150
550
150
220 400
mV
mV
ps
Dtr, Dtf Variation in Magnitude of Risetime and Falltime (Single−Ended) (See Figure 3b) Qx, Qx
125 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Measured by forcing VINPP (MIN) from a 50% duty cycle. Measurement taken with all outputs loaded 50 W to GND. Connect a 475 W resistor
from IREF (Pin 1) to GND. See Figure 6.
7. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per Figure 3.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
9. Skew is measured between outputs under identical transition conditions @ 50 MHz.
10. Phase noise integrated from 12 kHz to 20 MHz.
Qx
525 mV
CLK
CLK
tPLH
Q
Qx
VINPP = VIH(CLK) − VIL(CLK)
= VIH(CLK) − VIL(CLK)
Qx
175 mV
525 mV
tr
tf
tPHL
trMAX
175 mV
tfMAX
Qx
VOUTPP = VOH(Qx) − VOL(Qx)
= VOH(Qx) − VOL(Qx)
trMIN
trMAX − trMIN = Dtr
tfMIN
tfMAX − tfMIN = Dtf
(b) tr, tf and Dtr, Dtf
Qx
Q
DtPLH
DtPHL
(a) Propagation Delay and
Propagation Delay Variation
VCROSS
DVCROSS
Qx
Figure 3. AC Reference Measurement(c) VCROSS and DVCROSS
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| Information | Total 9 Pages | |
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