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NB3N106K fiches techniques PDF

ON Semiconductor - 3.3V Differential 1:6 Fanout Clock Driver

Numéro de référence NB3N106K
Description 3.3V Differential 1:6 Fanout Clock Driver
Fabricant ON Semiconductor 
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NB3N106K fiche technique
NB3N106K
3.3V Differential 1:6 Fanout
Clock Driver with HCSL
Outputs
Description
The NB3N106K is a differential 1:6 Clock fanout buffer with
Highspeed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N106K is designed
with HCSL PCI Express clock distribution and FBDIMM
applications in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL
signals per Figures 7, 8, and 9. Singleended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external Vth
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N106K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N106K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333, and
400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair
0.1 ps Typical Integrated Phase Jitter RMS
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Typical HCSL Output Levels (700 mV PeaktoPeak)
LVDS Output Levels with Interface Termination
These are PbFree Devices*
Applications
Clock Distribution
PCIe, II, III
Networking and Communications
High End Computing
End Products
Servers
FBDIMM Memory Cards
Ethernet Switch/Routers
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
QFN24
MN SUFFIX
CASE 485L
MARKING DIAGRAM*
NB3N
106K
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
Q0
Q0
Q1
CLK Q1
CLK
VTCLK
VCC
GND
IREF
RREF
Q4
Q4
Q5
Q5
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 5
1
Publication Order Number:
NB3N106K/D

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