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PDF CAT25M02 Data sheet ( Hoja de datos )
| Número de pieza | CAT25M02 | |
| Descripción | 2Mb SPI Serial CMOS EEPROM | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CAT25M02
2 Mb SPI Serial CMOS
EEPROM
Description
The CAT25M02 is a 2M−bit Serial CMOS EEPROM device
internally organized as 256Kx8 bits. This features a 256−byte page
write buffer and supports the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD input may be used to pause
any serial communication with the CAT25M02 device. The device
features software and hardware write protection, including partial as
well as full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• 5 / 10 MHz SPI Compatible
• Supply Voltage Range: 1.7 V to 5.5 V
• SPI Modes (0,0) & (1,1)
• 256−byte Page Write Buffer
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection – Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• 8−lead SOIC and 8−ball WLCSP Packages and Die Sales*
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25M02
SO
VSS
Figure 1. Functional Symbol
*Please contact factory for Die Sales Information
www.onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
WLCSP−8
C8A SUFFIX
CASE 567NM
PIN CONFIGURATIONS
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
SOIC (V) (Top View)
VCC
HOLD
CS
SO
SCK
SI
WP
VSS
WLCSP (C8A) (Top View)
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2016 − Rev. 2
1
Publication Order Number:
CAT25M02/D
1 page  
CAT25M02
Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25M02.
CS: The chip select input pin is used to enable/disable the
CAT25M02. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAT25M02 must
be preceded by a high to low transition and concluded with
a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25M02, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
VCC, either directly or through a resistor.
Functional Description
The CAT25M02 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 6.
Reading data stored in the CAT25M02 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25M02, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25M02 will accept any one of the six instruction
op−codes listed in Table 6 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
The CAT25M02 features an additional Identification
Page (256 bytes) which can be accessed for Read and Write
operations when the IPL bit from the Status Register is set
to “1”. The user can also choose to make the Identification
Page permanent write protected by setting the LIP bit from
the Status Register (LIP=“1”).
Table 6. INSTRUCTION SET
Instruction Opcode
Operation
WREN
0000 0110 Enable Write Operations
WRDI
0000 0100 Disable Write Operations
RDSR
0000 0101 Read Status Register
WRSR
0000 0001 Write Status Register
READ
0000 0011 Read Data from Memory
WRITE
0000 0010 Write Data to Memory
Figure 2. Synchronous Data Timing
www.onsemi.com
5
5 Page 
CAT25M02
Hold Operation
The HOLD input can be used to pause communication
between host and CAT25M02. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is
low.
Design Considerations
The CAT25M02 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
The CAT25M02 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
CS
SCK
HOLD
SO
tCD
tHD
tHZ
tHD
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
tCD
tLZ
www.onsemi.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CAT25M02.PDF ] | |
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