PDF NS9360 Data sheet ( Hoja de datos )

Número de pieza	NS9360
Descripción	CMOS network-attached processor
Fabricantes	Digi
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No Preview Available ! NS9360 Datasheet The Digi NS9360 is a single chip 0.13μm CMOS network-attached processor. The CPU is the ARM926EJ-S core with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard architecture. The NS9360 runs up to 177 MHz, with a 88 MHz system and memory bus and 44 MHz peripheral bus. The NS9360 operates at a 1.5V core and 3.3V I/O ring voltages. With its extensive set of I/O interfaces, Ethernet high-speed performance and processing NS9360 272 - pin BGA, lead-free, RoHS compliant capacity, the NS9360 is the most capable highly-integrated 32-bit network-attached processor available. The NS9360 is designed specifically for use in high- performance intelligent networked devices and Internet appliances including high- performance/low-latency remote I/O, intelligent networked information displays, and streaming and surveillance cameras. The NS9360 is a member of the award-winning NET+ARM USB Host USB Device 1284 Serial Module x4 UART SPI I2C LCD Controller 8 x Timers/Counters or 4 PWM ARM ARM926EJ-S 103 to 177 MHz 4K48kkBB I-Cache D-Cache JTAG Test and Debug Real Time Clock Distributed DMA 10/100 Ethernet MII/RMII MAC 50 to 90 MHz AMBA AHB Bus 32b-D, 32b-A Memory Controller CLK Generation Vectored Interrupt Controller Power Manager Ext. Peripheral Controller AHB Arbiter family of system-on-chip (SOC) solutions for embedded systems. 1 page NS9360 Features NS9360 Features 32-bit ARM926EJ-S RISC processor 103 to 177 MHz 5-stage pipeline with interlocking Harvard architecture 8 kB instruction cache and 4 kB data cache 32-bit ARM and 16-bit Thumb instruction sets. Can be mixed for performance/code density tradeoffs MMU to support virtual memory-based OSs such as Linux, WinCE/Pocket PC, VxWorks, others DSP instruction extensions, improved divide, single cycle MAC ARM Jazelle, 1200CM (coffee marks) Java accelerator EmbeddedICE-RT debug unit JTAG boundary scan, BSDL support External system bus interface 32-bit data, 32-bit internal address bus, 28-bit external address bus Glueless interface to SDRAM, SRAM, EEPROM, buffered DIMM, Flash 4 static and 4 dynamic memory chip selects 1-32 wait states per chip select A shared Static Extended Wait register allows transfers to have up to 16368 wait states that can be externally terminated. Self-refresh during system sleep mode Automatic dynamic bus sizing to 8 bits, 16 bits, 32 bits Burst mode support with automatic data width adjustment Two external DMA channels for external peripheral support System Boot High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending) High performance 10/100 Ethernet MAC 10/100 Mbps MII/RMII PHY interfaces Full-duplex or half-duplex Station, broadcast, or multicast address filtering 2 kB RX FIFO 256 byte TX FIFO with on-chip buffer descriptor ring – Eliminates underruns and decreases bus traffic Separate TX and RX DMA channels Intelligent receive-side buffer size selection Full statistics gathering support External CAM filtering support Flexible LCD controller Supports most commercially available displays: – 18-bit active Matrix color TFT displays – Single and dual panel color STN displays – Single and dual-panel monochrome STN displays Formats image data and generates timing control signals Internal programmable palette LUT and grayscaler support different color techniques Programmable panel-clock frequency www.digi.com 1 5 Page System configuration Register configuration: gpio 17, 12, 10, 8, 4 00101 Multiplier 1 Table 2: PLL ND[4:0] multiplier values These are sample frequency settings for each speed grade: 176.9472 MHz: pulldown gpio[12], gpio[10], gpio[4] 154.8288 MHz: pulldown gpio[12], gpio[10], gpio[8] 103.2192 MHz: pulldown gpio[17], gpio[10], gpio[8], gpio[4] There are 32 additional GPIO pins that are used to create a general purpose, user-defined ID register. These are external signals that are registered at powerup. gpio[41] gpio[37] gpio[33] gpio[29] gpio[25] gpio[18] gpio[13] gpio[6] gpio[40] gpio[36] gpio[32] gpio[28] gpio[23] gpio[16] gpio[11] gpio[5] gpio[39] gpio[35] gpio[31] gpio[27] gpio[22] gpio[15] gpio[9] gpio[3] gpio[38] gpio[34] gpio[30] gpio[26] gpio[21] gpio[14] gpio[7] gpio[1] Read these signals for general purpose status information. www.digi.com 7 11 Page

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