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PDF EN25QH32 Data sheet ( Hoja de datos )
| Número de pieza | EN25QH32 | |
| Descripción | 32 Megabit Serial Flash Memory | |
| Fabricantes | Eon Silicon Solution | |
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EN25QH32
EN25QH32
32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• 32 M-bit Serial Flash
- 32 M-bit/4,096 K-byte/16,384 pages
- 256 bytes per programmable page
• Standard, Dual or Quad SPI
- Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD#
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
• High performance
- 104MHz clock rate for Standard SPI
- 80MHz clock rate for two data bits
- 50MHz clock rate for four data bits
• Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
• Uniform Sector Architecture:
- 1024 sectors of 4-Kbyte
- 64 blocks of 64-Kbyte
- Any sector or block can be erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Page program time: 1.3ms typical
- Sector erase time: 90ms typical
- Block erase time 500ms typical
- Chip erase time: 25 seconds typical
• Lockable 512 byte OTP security sector
• Support Serial Flash Discoverable
Parameters (SFDP) signature
• Read Unique ID Number
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- 16 pins SOP 300mil body width
- 24 balls TFBGA (6x8mm)
- All Pb-free packages are RoHS compliant
• Industrial temperature Range
GENERAL DESCRIPTION
The EN25QH32 is a 32 Megabit (4,096 K-byte) Serial Flash memory, with enhanced write protection
mechanisms. The EN25QH32 supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select,
Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 80MHz are
supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output when using the Dual
Output Fast Read instructions, and SPI clock frequencies of up to 50MHz are supported allowing
equivalent clock rates of 200MHz (50MHz x 4) for Quad Output when using the Quad Output Fast
Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The EN25QH32 is designed to allow either single Sector/Block at a time or full chip erase operation.
The EN25QH32 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
1 page  
Table 1. Pin Names
EN25QH32
Symbol
CLK
DI (DQ0)
DO (DQ1)
CS#
WP# (DQ2)
HOLD# (DQ3)
Vcc
Vss
NC
Pin Name
Serial Clock Input
Serial Data Input (Data Input Output 0) *1
Serial Data Output (Data Input Output 1) *1
Chip Select
Write Protect (Data Input Output 2) *2
HOLD# pin (Data Input Output 3) *2
Supply Voltage (2.7-3.6V)
Ground
No Connect
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ2 ~ DQ3 are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25QH32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
5 Page 
EN25QH32
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate)
by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ
(EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ
(EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output
FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the
QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output
FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection
since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ
(EBh) will be always available in EQPI mode.
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25QH32 provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
11 Page | ||
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| PDF Descargar | [ Datasheet EN25QH32.PDF ] | |
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