DataSheet.es    


PDF KSZ8895MLU Data sheet ( Hoja de datos )

Número de pieza KSZ8895MLU
Descripción Integrated 5-Port 10/100 Managed Switch
Fabricantes Micrel Semiconductor　
Logotipo Micrel Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de KSZ8895MLU (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! KSZ8895MLU Hoja de datos, Descripción, Manual

KSZ8895MLU
Integrated 5-Port 10/100 Managed Switch
General Description
The KSZ8895MLU is a highly-integrated Layer 2-managed
5-port switch with an optimized design and plentiful
features. It is designed for cost-sensitive 10/100Mbps 5-
port switch systems with on-chip termination, lowest power
consumption and internal core power controller. These
features will save more system cost. It has 1.4Gbps high-
performance memory bandwidth, shared memory based
switch fabric with full non-blocking configuration. It also
provides an extensive feature set such as power
management, programmble rate limit and priority ratio,
tag/port-based VLAN, packets filtering, quality of service
(QoS) four-queues prioritization, management interface,
and MIB counters. Port 5 is a MAC 5 MII interface with
PHY mode. The SW5-MII interface can be connected to a
processor with a MAC MII interface.
The KSZ8895MLU provides multiple CPU control/data
interfaces to effectively address both current and emerging
fast Ethernet applications.
The KSZ8895MLU consists of 10/100 PHYs with patented
and enhanced mixed-signal technology, media access
control (MAC) units, a high-speed non-blocking switch
fabric, a dedicated address lookup engine, and an on-chip
frame buffer memory. The KSZ8895MLU contains five
MACs and four intergrated PHYs. All PHYs support
10/100Base-T/TX.
All registers of MACs and PHYs units can be managed by
the SPI interface or the SMI interface. MIIM registers of the
PHYs can be accessed through the MDC/MDIO interface.
EEPROM can set all control registers for the unmanaged
mode.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2011
M9999-051111-1.0

1 page




KSZ8895MLU pdf
Micrel, Inc.
KSZ8895MLU
IGMP Support ................................................................................................................................................................... 34
Port Mirroring Support ...................................................................................................................................................... 35
VLAN Support ................................................................................................................................................................... 35
Rate Limiting Support ....................................................................................................................................................... 36
Ingress Rate Limit ............................................................................................................................................................. 36
Egress Rate Limit.............................................................................................................................................................. 36
Transmit Queue Ratio Programming ................................................................................................................................ 37
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ........................ 37
Configuration Interface ..................................................................................................................................................... 37
Register Description ........................................................................................................................................................... 43
Global Registers.................................................................................................................................................................. 45
Port Registers...................................................................................................................................................................... 55
Advanced Control Registers.............................................................................................................................................. 65
Data Rate Selection Table in 100BT .................................................................................................................................. 82
Data Rate Selection Table in 10BT .................................................................................................................................... 82
Static MAC Address Table ................................................................................................................................................. 84
VLAN Table .......................................................................................................................................................................... 86
Dynamic MAC Address Table ............................................................................................................................................ 89
Management Information Base (MIB) Counters............................................................................................................... 91
MIIM Registers ..................................................................................................................................................................... 95
Absolute Maximum Ratings(1) ............................................................................................................................................ 99
Operating Ratings(2) ............................................................................................................................................................ 99
Electrical Characteristics(4, 5).............................................................................................................................................. 99
Timing Diagrams ............................................................................................................................................................... 101
EEPROM Timing............................................................................................................................................................. 101
SNI Timing ...................................................................................................................................................................... 102
MII Timing ....................................................................................................................................................................... 103
SPI Timing ...................................................................................................................................................................... 104
Auto-Negotiation Timing ................................................................................................................................................. 106
Reset Timing................................................................................................................................................................... 107
Reset Circuit Diagram..................................................................................................................................................... 108
Isolation Transformer Selection ...................................................................................................................................... 109
Reference Crystal Selection............................................................................................................................................. 109
Package Information......................................................................................................................................................... 110
May 2011
5 M9999-051111-1.0

5 Page





KSZ8895MLU arduino
Micrel, Inc.
KSZ8895MLU
Pin Description (Continued)
Pin Number
Pin Name
Type(1)
63
PMRXD2
IPD/O
64
PMRXD1
IPD/O
65
PMRXD0
IPD/O
66
PMRXER
IPD/O
67
PCRS
IPD/O
68
PCOL
IPD/O
69
SMTXEN
IPD
70
SMTXD3
IPD
71
SMTXD2
IPD
72
SMTXD1
IPD
73
SMTXD0
IPD
74
SMTXER
IPD
75
SMTXC
I/O
76
GNDD
GND
77
VDDIO
P
78
SMRXC
I/O
79
SMRXDV
IPD/O
80
SMRXD3
IPD/O
Port
5
5
5
5
5
5
Pin Function(2)
Reserved for MLU.
Strap option:
PD (default) = disable back pressure.
PU = enable back pressure.
Reserved for MLU.
Strap option:
PD (default) = drop excessive collision packets.
PU = does not drop excessive collision packets.
Reserved for MLU.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex mode.
PU = enable for performance enhancement.
Reserved for MLU.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
Reserved for MLU.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register
76.
Reserved for MLU.
Strap option for port 4 only.
PD (default) = no force flow control, normal operation.
PU = force flow control. Refer to Register 66.
Port 5 Switch MII transmit enable.
Port 5 Switch MII transmit bit 3.
Port 5 Switch MII transmit bit 2.
Port 5 Switch MII transmit bit 1.
Port 5 Switch MII transmit bit 0.
Port 5 Switch MII transmit error.
Port 5 Switch MII transmit clock:
Input: SW5-MII MAC mode.
Output: SW5-MII PHY modes.
Digital ground.
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
Port 5 Switch MII receive clock:
Input: SW5-MII MAC mode.
Output: SW5-MII PHY mode.
Switch MII receive data valid.
Port 5 Switch MII receive bit 3.
Strap option:
PD (default) = Disable Switch SW5-MII full-duplex flow control
PU = Enable Switch SW5-MII full-duplex flow control.
May 2011
11 M9999-051111-1.0

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet KSZ8895MLU.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
KSZ8895MLUIntegrated 5-Port 10/100 Managed SwitchMicrel Semiconductor
Micrel Semiconductor
KSZ8895MLUBIntegrated 5-Port 10/100 Managed SwitchMicrel Semiconductor
Micrel Semiconductor
KSZ8895MLXIntegrated 5-Port 10/100 Managed Ethernet SwitchMicrochip
Microchip

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar