|
|
PDF KSZ8851-16MLLU Data sheet ( Hoja de datos )
| Número de pieza | KSZ8851-16MLLU | |
| Descripción | Single-Port Ethernet MAC Controller | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de KSZ8851-16MLLU (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
KSZ8851-16MLL/MLLI/MLLU
Single-Port Ethernet MAC Controller
with 8-Bit or 16-Bit Non-PCI Interface
Revision 2.3
General Description
The KSZ8851M-series is a single-port controller chip with
a non-PCI CPU interface and is available in 8-bit and 16-
bit bus designs. This datasheet describes the 48-pin LQFP
KSZ8851-16MLL for applications requiring high-
performance from a single-port Ethernet controller with an
8-bit or 16-bit generic processor interface. The KSZ8851-
16MLL offers the most cost-effective solution for adding
high-throughput Ethernet connectivity to traditional
embedded systems.
The KSZ8851-16MLL is a single chip, mixed analog/digital
device offering wake-on-LAN technology for effectively
addressing fast Ethernet applications. It consists of a fast
Ethernet MAC controller, an 8-bit or 16-bit generic host
processor interface, and incorporates a unique, dynamic
memory pointer with 4-byte buffer boundary and a fully
utilizable 18KB for both TX (allocated 6KB) and RX
(allocated 12KB) directions in the host buffer interface.
The KSZ8851-16MLL is designed to be fully compliant with
the appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8851-16MLLI and a
qualified AEC-Q100 automotive version of the KSZ8851-
16MLLU are also available (see the Ordering Information
section).
LinkMD®
Physical signal transmission and reception are enhanced
through the use of analog circuitry. This makes the design
more efficient and allows lower-power consumption. The
KSZ8851-16MLL is designed using a low-power CMOS
process that features a single 3.3V power supply with
options for 1.8V, 2.5V, or 3.3V VDD I/O. The device
includes an extensive feature set that offers management
information base (MIB) counters and CPU control/data
interfaces with single shared data bus timing.
The KSZ8851-16MLL includes a unique cable diagnostics
feature called LinkMD®. This feature determines the length
of the cabling plant and also ascertains if there is an open
or short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8851-16MLL
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Datasheets and support documentation are available on
Micrel’s website at: www.micrel.com.
Functional Diagram
Figure 1. KSZ8851-16MLL/MLLI Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 12, 2015
Revision 2.3
1 page  
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
Contents
List of Figures.......................................................................................................................................................................... 8
List of Tables ........................................................................................................................................................................... 9
Pin Configuration................................................................................................................................................................... 10
Pin Description ...................................................................................................................................................................... 11
Pin for Strap-In Options......................................................................................................................................................... 14
Functional Description........................................................................................................................................................... 15
Fuctional Overview................................................................................................................................................................ 15
Power Management ..................................................................................................................................................... 15
Normal Operation Mode ............................................................................................................................................... 15
Energy Detect Mode..................................................................................................................................................... 15
Soft Power-Down Mode................................................................................................................................................ 16
Power-Saving Mode ..................................................................................................................................................... 16
Wake-on-LAN ............................................................................................................................................................... 16
Detection of Energy ...................................................................................................................................................... 16
Detection of Linkup....................................................................................................................................................... 16
Wake-up Packet ........................................................................................................................................................... 16
Magic Packet™ ............................................................................................................................................................ 17
Physical Layer Transceiver (PHY)
18
100BASE-TX Transmit ................................................................................................................................................. 18
100BASE-TX Receive .................................................................................................................................................. 18
PLL Clock Synthesizer (Recovery)............................................................................................................................... 18
Scrambler/De-scrambler (100BASE-TX only) .............................................................................................................. 18
10BASE-T Transmit...................................................................................................................................................... 18
10BASE-T Receive....................................................................................................................................................... 18
MDI/MDI-X Auto Crossover .......................................................................................................................................... 19
Straight Cable ............................................................................................................................................................... 19
Crossover Cable ........................................................................................................................................................... 20
Auto Negotiation ........................................................................................................................................................... 20
LinkMD® Cable Diagnostics.......................................................................................................................................... 22
Access .......................................................................................................................................................................... 22
Usage ........................................................................................................................................................................... 22
Media Access Control (MAC) Operation
23
Inter Packet Gap (IPG) ................................................................................................................................................. 23
Back-Off Algorithm ....................................................................................................................................................... 23
Late Collision ................................................................................................................................................................ 23
Flow Control.................................................................................................................................................................. 23
Half-Duplex Backpressure............................................................................................................................................ 23
Address Filtering Function............................................................................................................................................ 23
Clock Generator ........................................................................................................................................................... 24
Bus Interface Unit (BIU)
25
Supported Transfers..................................................................................................................................................... 25
Physical Data Bus Size ................................................................................................................................................ 25
Little and Big Endian Support ....................................................................................................................................... 25
Asynchronous Interface................................................................................................................................................ 26
BIU Summation ............................................................................................................................................................ 26
Queue Management Unit (QMU) .......................................................................................................................................... 27
Transmit Queue (TXQ) Frame Format.......................................................................................................................... 27
Frame Transmitting Path Operation in TXQ ................................................................................................................. 28
Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLL ............................................................ 29
Frame Queue (RXQ) Frame Format............................................................................................................................. 30
Frame Receiving Path Operation in RXQ .................................................................................................................... 30
Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor ............................................................. 31
EEPROM Interface................................................................................................................................................................ 32
March 12, 2015
5
Revision 2.3
5 Page 
Micrel, Inc.
KSZ8851-16MLL/MLLI/MLLU
Pin Description
Pin Number Pin Name
1 P1LED1
2 P1LED0
3 PME
Type(1)
IPU/O
OPU
OPU
Pin Function
Programmable LED output to indicate port activity/status.
LED is ON when output is LOW; LED is OFF when output is HIGH.
Port 1 LED indicators* defined as follows:
Chip Global Control Register: CGCR bit [9]
0 (Default)
1
P1LED1 100BT
ACT
P1LED0 LINK/ACT
LINK
* Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;
Speed = LED On (100BASE-T); LED Off (10BASE-T)
Config Mode: The P1LED1 pull-up/pull-down value is latched as 16-/8-bit mode during
power-up/reset. See the Pin for Strap-In Options section for details
Power Management Event (default active low): It is asserted (low or high depends on
polarity set in PMECR register) when one of the wake-on-LAN events is detected by
KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low
power mode.
4
INTRN
OPU
Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin
need an external 4.7K pull-up resistor.
Read Strobe Not
5
RDN
IPU
Asynchronous read strobe, active low to indicate read cycle.
Write Strobe Not
6
WRN
IPU
Asynchronous write strobe, active low to indicate write cycle.
7
DGND
GND Digital ground
1.8V regulator output . This 1.8V output pin provides power to pins 14 (VDD_A1.8) and 29
(VDD_D1.8) for core VDD supply.
8 VDD_CO1.8 P If VDD_IO is set for 1.8V then this pin should be left floating, pins 14 (VDD_A1.8) and 29
(VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 27, 38 and 46
(VDD_IO) with appropriate filtering.
In/Out Data from/to external EEPROM.
9
EED_IO
IPD/O Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during
power-up/reset. See the Pin for Strap-In Options section for details
Notes:
1. P = Power supply
GND = Ground
I/O = Bi-directional
I = Input
O = Output.
IPD = Input with internal pull-down (58K ±30%).
IPU = Input with internal pull-up (58K ±30%).
OPD = Output with internal pull-down (58K ±30%).
OPU = Output with internal pull-up (58K ±30%).
IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.
IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.
I/O (PD) = Input/Output with internal pull-down (58K ±30%).
March 12, 2015
11
Revision 2.3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8851-16MLLU.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KSZ8851-16MLL | Single-Port Ethernet MAC Controller | Micrel Semiconductor |
| KSZ8851-16MLLI | Single-Port Ethernet MAC Controller | Micrel Semiconductor |
| KSZ8851-16MLLU | Single-Port Ethernet MAC Controller | Micrel Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |