FIN1049 Datasheet PDF - Fairchild Semiconductor
| Part Number | FIN1049 | |
| Description | LVDS Dual Line Driver | |
| Manufacturers | Fairchild Semiconductor | |
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March 2003
Revised March 2003
FIN1049
LVDS Dual Line Driver with Dual Line Receiver
General Description
This dual Driver-Receiver is designed for high speed inter-
connects utilizing Low Voltage Differential Signaling
(LVDS) technology. The Driver accepts LVTTL inputs and
translates them to LVDS outputs. The Receiver accepts
LVDS inputs and translates them to LVTTL outputs. The
LVDS levels have a typical differential output swing of
350mV which provide for low EMI at ultra low power dissi-
pation even at high frequencies. The FIN1049 can accept
LVPECL inputs for translating from LVPECL to LVDS. The
En and Enb inputs are ANDed together to enable/disable
the outputs. The enables are common to all four outputs. A
single line driver and single line receiver function is also
available in the FIN1019.
Features
s Greater than 400 Mbps data rate
s 3.3V power supply operation
s Low power dissipation
s Fail safe protection for open-circuit conditions
s Meets or exceeds the TIA/EIA-644-A LVDS standard
s 16-pin TSSOP package saves space
s Flow-through pinout simplifies PCB layout
s Enable/Disable for all outputs
s Industrial operating temperature range:
−40°C to +85°C
Ordering Code:
Order Number Package Number
Package Description
FIN1049MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Name
Description
RIN1+, RIN2+ Non-Inverting LVDS Inputs
RIN1−, RIN2− Inverting LVDS Inputs
DOUT1+, DOUT2+ Non-Inverting Driver Outputs
DOUT1−, DOUT2− Inverting Driver Outputs
EN, ENb Driver Enable Pins for All Outputs
ROUT1, ROUT2
DIN2, DIN2
VCC
GND
LVTTL Output Pins for ROUT1 and ROUT2
LVTTL Input Pins for DIN1 and DIN2
Power Supply (3.3V)
Ground
© 2003 Fairchild Semiconductor Corporation DS500846
www.fairchildsemi.com
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Required Specifications
1. Human Body Model ESD and Machine Model ESD
should be measured using MIL-STD-883C method
3015.7 standard.
2. Latch-up immunity should be tested to the EIA/JEDEC
Standard Number 78 (EIA/JESD78).
Note: CL = 15pF, includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
VIA
1.25
1.15
VCC
VCC - 0.1
0.1
0.0
1.75
0.65
VCC
VCC - 1.1
1.1
0.0
VIB
1.15
1.25
VCC - 0.1
VCC
0.0
0.1
0.65
1.75
VCC - 1.1
VCC
0.0
1.1
Resulting Differential Input
Voltage (mV)
VID
100
−100
100
−100
100
−100
1100
−1100
1100
−1100
1100
−1100
Resulting Common
Mode Input Voltage (V)
VIC
1.2
1.2
VCC - 0.05
VCC - 0.05
0.05
0.05
1.2
1.2
VCC - 0.55
VCC - 0.55
0.55
0.55
Note: RL = 100Ω
FIGURE 2. LVDS Output Circuit for DC Test
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for FIN1049 electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ FIN1049.PDF Datasheet ] | |
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