PDF EDJ4208EFBG-L Data sheet ( Hoja de datos )

Número de pieza	EDJ4208EFBG-L
Descripción	64 Meg x 8 x 8 banks DDR3L-RS SDRAM
Fabricantes	Micron
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No Preview Available ! 4Gb: x8, x16 DDR3L-RS SDRAM Description DDR3L-RS SDRAM EDJ4208EFBG-L – 64 Meg x 8 x 8 banks EDJ4216EFBG-L – 32 Meg x 16 x 8 banks Description The 1.35V DDR3L-RS SDRAM device is a low-voltage version of the DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V-compatible mode. Features • VDD = VDDQ = 1.35V (1.283–1.45V) • Backward compatible to VDD = VDDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward com- patible in 1.5V applications • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • Programmable partial-array self refresh (PASR) • Reduced self refresh current – IDD6: 2.2mA (TYP) at 25ºC • TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C • Self refresh temperature (SRT) • Automatic self refresh (ASR) • Write leveling • Multipurpose register • Output driver calibration Options • Configuration – 512 Meg x 8 – 256 Meg x 16 • FBGA package (Pb-free) – x8 – 78-ball (9mm x 10.6mm) Rev. F • FBGA package (Pb-free) – x16 – 96-ball FBGA (9mm x 13.5mm) Rev. F • Timing – cycle time – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) • Operating temperature – Commercial (0°C ≤ TC ≤ +95°C)1 • Revision: F Note: 1. No guarantee on industrial and automotive temperature ranges. Table 1: Key Timing Parameters Speed Grade -GN2 -DJ1 Data Rate (MT/s) 1600 1333 Target tRCD-tRP-CL 11-11-11 9-9-9 Notes: 1. Backward compatible to 1066, CL = 7. 2. Backward compatible to 1333, CL = 9. Table 2: Addressing Parameter Configuration Refresh count 512 Meg x 8 64 Meg x 8 x 8 banks 8K tRCD (ns) 13.75 13.5 tRP (ns) 13.75 13.5 CL (ns) 13.75 13.5 256 Meg x 16 32 Meg x 16 x 8 banks 8K PDF: 09005aef859bddc0 4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1 page 4Gb: x8, x16 DDR3L-RS SDRAM Description ODT Latency and Posted ODT .................................................................................................................... 190 Timing Parameters .................................................................................................................................... 190 ODT Off During READs .............................................................................................................................. 193 Asynchronous ODT Mode .............................................................................................................................. 195 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 197 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 199 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 201 Revision History ............................................................................................................................................ 204 Rev. A – 03/14 ............................................................................................................................................ 204 PDF: 09005aef859bddc0 4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 5 Page State Diagram 4Gb: x8, x16 DDR3L-RS SDRAM State Diagram Figure 2: Simplified State Diagram Power applied Power on Reset procedure From any state RESET Initial- ization ZQCL MRS, MPR, write leveling MRS ZQ ZQCL/ZQCS calibration Idle SRE SRX REF CKE L Self refresh Refreshing Active power- down CKE L PDX PDE PDE ACT PDX Activating Precharge power- down CKE L WRITE Writing WRITE Bank active READ WRITE AP WRITE READ AP READ READ Reading WRITE AP Writing WRITE AP READ AP PRE, PREA PRE, PREA PRE, PREA READ AP Reading ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PDF: 09005aef859bddc0 4Gb_DDR3L_RS_F_EDJ.pdf - Rev. A 4/14 EN Precharging PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry Automatic sequence Command sequence SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 11 Page

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