C8051F520A-IM Datasheet PDF - Silicon Laboratories
| Part Number | C8051F520A-IM | |
| Description | 8/4/2 kB ISP Flash MCU | |
| Manufacturers | Silicon Laboratories | |
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There is a preview and C8051F520A-IM download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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Analog Peripherals
- 12-Bit ADC
• Programmable throughput up to 200 ksps
• Up to 6/16 external inputs
• Data dependent windowed interrupt generator
• Built-in temperature sensor
- Comparator
• Programmable hysteresis and response time
• Configurable as wake-up or reset source
• Low current
- POR/Brownout Detector
- Voltage Reference—1.5 and 2.2 V
(programmable)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Supply Voltage 2.0 to 5.25 V
- Built-in LDO regulator
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with
25 MHz system clock
- Expanded interrupt handler
C8051F52x/F53x
8/4/2 kB ISP Flash MCU Family
Memory
- 8/4/2 kB Flash; In-system byte programmable in
512 byte sectors
- 256 bytes internal data RAM
Digital Peripherals
- 16/6 port I/O; push-pull or open-drain, 5 V tolerant
- Hardware SPI™, and UART serial port
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Three general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
Clock Sources
- Internal oscillators: 24.5 MHz ±0.5% accuracy sup-
ports UART and LIN-Master operation
- External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly
Packages
- 10-Pin DFN (3 x 3 mm)
- 20-pin QFN (4 x 4 mm)
- 20-pin TSSOP
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
Rev. 1.4 4/12
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
+
-
TEMP
SENSOR
VOLTAGE
COMPARATOR
VREF VREG
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
Port 1
LIN
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Copyright © 2012 by Silicon Laboratories
C8051F52x/F53x
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C8051F52x/F52xA/F53x/F53xA
14.2.2. External Crystal Example...................................................................... 139
14.2.3. External RC Example............................................................................ 141
14.2.4. External Capacitor Example.................................................................. 141
14.3. System Clock Selection................................................................................. 143
15. UART0 ................................................................................................................... 144
15.1. Enhanced Baud Rate Generation.................................................................. 145
15.2. Operational Modes ........................................................................................ 146
15.2.1. 8-Bit UART ............................................................................................ 146
15.2.2. 9-Bit UART ............................................................................................ 147
15.3. Multiprocessor Communications ................................................................... 148
16. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 151
16.1. Signal Descriptions........................................................................................ 152
16.1.1. Master Out, Slave In (MOSI)................................................................. 152
16.1.2. Master In, Slave Out (MISO)................................................................. 152
16.1.3. Serial Clock (SCK) ................................................................................ 152
16.1.4. Slave Select (NSS) ............................................................................... 152
16.2. SPI0 Master Mode Operation ........................................................................ 153
16.3. SPI0 Slave Mode Operation .......................................................................... 154
16.4. SPI0 Interrupt Sources .................................................................................. 155
16.5. Serial Clock Timing........................................................................................ 156
16.6. SPI Special Function Registers ..................................................................... 156
17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A) .......................... 164
17.1. Software Interface with the LIN Peripheral .................................................... 165
17.2. LIN Interface Setup and Operation................................................................ 165
17.2.1. Mode Definition ..................................................................................... 165
17.2.2. Baud Rate Options: Manual or Autobaud ............................................. 165
17.2.3. Baud Rate Calculations—Manual Mode ............................................... 165
17.2.4. Baud Rate Calculations—Automatic Mode ........................................... 168
17.3. LIN Master Mode Operation .......................................................................... 169
17.4. LIN Slave Mode Operation ............................................................................ 170
17.5. Sleep Mode and Wake-Up ............................................................................ 171
17.6. Error Detection and Handling ........................................................................ 171
17.7. LIN Registers................................................................................................. 172
17.7.1. LIN Direct Access SFR Registers Definition ......................................... 172
17.7.2. LIN Indirect Access SFR Registers Definition....................................... 174
18. Timers ................................................................................................................... 182
18.1. Timer 0 and Timer 1 ...................................................................................... 182
18.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 182
18.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 184
18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 184
18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 185
18.2. Timer 2 .......................................................................................................... 190
18.2.1. 16-bit Timer with Auto-Reload............................................................... 190
18.2.2. 8-bit Timers with Auto-Reload............................................................... 191
18.2.3. External Capture Mode ......................................................................... 192
Rev. 1.4
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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