R5F563TEBDFH Datasheet PDF - Renesas
| Part Number | R5F563TEBDFH | |
| Description | MCUs | |
| Manufacturers | Renesas | |
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Features
DATASHEET
RX63T Group
Renesas MCUs
R01DS0087EJ0210
Rev.2.10
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
Sep 26, 2013
Two 12-bit ADCs (three S/H circuits, double data registers, amplifier, comparator), one 10-bit ADC, simultaneous
sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase
complementary channels or 3 three-phase complementary channels + 1 single-phase complementary channel)
Features
■ 32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
■ Low-power design and architecture
Single 3.3-V supply or single 5-V supply; 3.3-V products can be
used with a 5-V analog power supply
Four low-power modes
■ On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
Max. 512 Kbytes
User code is programmable by USB, SCI, or JTAG.
■ On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
Max. 48 Kbytes
For instructions and operands
■ DMA
DMA: Incorporates four channels
DTC: A single unit can handle transfer on multiple channels.
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
External crystal oscillator or internal PLL for operation at 4 to 12.5
MHz
Internal 125-kHz LOCO
Dedicated 125-kHz LOCO for the IWDT
■ Independent watchdog timer
125-kHz LOCO clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
■ External address space
4 CS areas (4 × 1 Mbyte)
Multiplexed address data or separate address lines are selectable per
area.
8- or 16-bit bus space is selectable per area.
PLQP0144KA-A 20 × 20mm, 0.5mm pitch
PLQP0120KA-A 16 × 16mm, 0.5mm pitch
PLQP0112JA-A 20 × 20mm, 0.65mm pitch
PLQP0100KB-A 14 × 14mm, 0.5mm pitch
PLQP0064KB-A 10 × 10mm, 0.5mm pitch
PLQP0048KB-A 7 × 7mm, 0.5mm pitch
■ Up to 11 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (1
channel)
SCI with multiple functionalities (5 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simple SPI, simple I2C, and extended
serial mode.
I2C bus interface for SMBus (2 channels)
RSPI for high-speed transfer (2 channels)
■ Up to twenty 16-bit timers
16-bit MTU3: 100-MHz operation, input capture, output compare,
three-phase complementary PWM waveform output (2 channels),
phase-counting mode (8 channels); complementary PWM does not
burden the CPU.
16-bit GPT: 100-MHz operation, input capture, output compare, 4-
channel single-phase complementary PWM waveform output or 1-
channel three-phase complementary + 1-channel single-phase
complementary output, interlocking with comparator (counter
operation, PWM negation control), detection of abnormal oscillation
frequencies (useful for IEC60730 compliance)
(8 channels); complementary PWM does not burden the CPU.
16-bit CMT (4 channels)
■ Generation of delays in PWM waveforms (for
products with the product ID code 1)
The timing with which signals on the 16-bit GPT PWM output pin
rise and fall can be controlled with an accuracy of up to 312 ps (in
operation at 100 MHz).
■ Two A/D converters for 1-MHz operation, total of 8
channels
Simultaneous sampling on 7 channels is possible with three units.
Self-diagnosis function (useful for IEC60730 compliance)
Two 12-bit ADCs: three sample-and-hold circuits, double data
registers, amplifier, comparator (8 channels)
One 10-bit ADC (12 channels)
■ One A/D converter for 2-MHz operation, total of 20
channels
One 10-bit ADC (20 channels)
■ 10-bit D/A converter: 2 channels
■ Digital Power Supply Controller-Dedicated
Calculation Function (for products with product ID
code 1)
16-bit fixed-point calculation function that handles compensatory
calculations in the method of digital control for switched-mode
power supplies.
■ Register write protection function can protect values
in important registers against overwriting.
■ Up to 110 pins for GPIO
Open drain, switchable driving ability
■ Operating temp. range
–40C to +85C
–40C to +105C
R01DS0087EJ0210 Rev.2.10
Sep 26, 2013
Page 1 of 182
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RX63T Group
1. Overview
Table 1.1
Outline of Specifications (4/7)
Classification
Timers
Module/Function
General PWM timer
(GPT)
Compare match timer
(CMT)
Watchdog timer
(WDTA)
Independent watchdog
timer (IWDTa)
Communication USB 2.0 host/function
function
module (USBa)
Serial communications
interfaces (SCIc, SCId)
Description
16 bits x 8 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Select from among four count clocks (PCLKA/1, PCLKA/4, PCLKA/8, and PCLKA/16)
for each channel
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: Output of the internal comparator detection, software, and
compare-match
The main clock can be used as a counter clock for measuring the timing of the edges of
signals produced by frequency-dividing the dedicated clock signal for the IWDT (to
detect abnormal oscillation).
A PWM delay with an accuracy of up to 1/32 times the period of the system clock (ICLK)
can be generated to control the timing with which signals from the two PWM output pins
from each of channels 0 to 3 rise and fall.
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
14 bits × 1 channel
Counter-input clock: Dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power mode are selectable
Supports the OTG (On-The-Go)
Incorporates 2 Kbytes of RAM as a transfer buffer
5 channels (SCIc: 4 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Simple I2C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
R01DS0087EJ0210 Rev.2.10
Sep 26, 2013
Page 5 of 182
Preview 5 Page |
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