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PDF 64F7054 Data sheet ( Hoja de datos )
| Número de pieza | 64F7054 | |
| Descripción | HD64F7054 | |
| Fabricantes | Renesas Technology | |
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The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Hitachi SuperHTM RISC engine
SH-2
SH7052 F-ZTAT™
SH7053 F-ZTAT™
SH7054 F-ZTAT™
Hardware Manual
ADE-602-185B
Rev. 3.0
3/3/03
Hitachi, Ltd.
1 page  
Main Revisions and Additions in this Edition
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Revisions (See Manual for Details)
8 1.3.1 Pin Arrangement
Name of 155 th pin amended (PK11/TO8L)
61 5.1.1 Types of Exception
Processing and Priority
Table 5.1 Types of Exception Processing and Priority
Order
Compare match timer (CMT1), A/D converter channel 1
(A/D1) added
Module abbreviations amended: CMT0, A/D0
160 9.3.5 Dual Address Mode
Figure 9.5 Dual Address Mode and Indirect Address
Operation (16-Bit-Width External Memory Space)
Description of 1st and 2nd bus cycles amended
If the data bus is 16 bits wide when the external
memory space is accessed, two bus cycles are
necessary.
217 10.2.3 Timer Control Registers Timer Control Register 9A, 9B, 9C (TCR9A, TCR9B,
(TCR)
TCR9C) Description of Bits 1 and 0 amended
x=A, C, or E
306 10.2.15 Free-Running Counters Description of Free-Running Counter 0 added
(TCNT)
When the bits corresponding to the timer start register 1
(TSTR1) are set to 1, this counter starts to count.
307 Description of Free-Running Counters 1A, 1B, 2A, 2B,
3, 4, 5, 11 added
When the bits corresponding to the timer start register
1, 3 (TSTR1, TSTR3) are set to 1, these counters start
to count.
335 10.3.1 Overview
Description of Channel 2 amended
337 Description of Channel 10 amended
348 10.3.9 PWM Timer Function Description amended
..., and H'0002, H'0003, H'0004 (100%), and H'0000
(0%) in BFR6A.
375 10.6 Sample Setup Procedures Sample Setup Procedure for Channel 0 Input Capture
Triggered by Channel 10 Compare-Match
Register name amended
399 Writing to ROM Area
Description added
Immediately after ATU Register
Write
5 Page 
6.3.3 IRQ Status Register (ISR) ....................................................................................
6.4 Interrupt Operation ............................................................................................................
www.dat6a.s4h.e1et4uI.ncotemrrupt Sequence................................................................................................
6.4.2 Stack after Interrupt Exception Processing ..........................................................
6.5 Interrupt Response Time ...................................................................................................
6.6 Data Transfer with Interrupt Request Signals ...................................................................
6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ...............
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................
90
92
92
94
95
97
97
97
Section 7 User Break Controller (UBC) ..................................................................... 99
7.1 Overview............................................................................................................................ 99
7.1.1 Features ................................................................................................................ 99
7.1.2 Block Diagram...................................................................................................... 100
7.1.3 Register Configuration ......................................................................................... 101
7.2 Register Descriptions......................................................................................................... 101
7.2.1 User Break Address Register (UBAR)................................................................. 101
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 102
7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 104
7.2.4 User Break Control Register (UBCR).................................................................. 106
7.3 Operation ........................................................................................................................... 107
7.3.1 Flow of the User Break Operation........................................................................ 107
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 109
7.3.3 Program Counter (PC) Values Saved ................................................................... 109
7.4 Examples of Use................................................................................................................ 110
7.4.1 Break on CPU Instruction Fetch Cycle ................................................................ 110
7.4.2 Break on CPU Data Access Cycle........................................................................ 111
7.4.3 Break on DMA Cycle........................................................................................... 111
7.5 Usage Notes ....................................................................................................................... 112
7.5.1 Simultaneous Fetching of Two Instructions......................................................... 112
7.5.2 Instruction Fetch at Branches ............................................................................... 112
7.5.3 Contention between User Break and Exception Processing ................................ 113
7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 113
7.5.5 User Break Trigger Output................................................................................... 113
7.5.6 Module Standby.................................................................................................... 114
Section 8 Bus State Controller (BSC) ......................................................................... 115
8.1 Overview............................................................................................................................ 115
8.1.1 Features ................................................................................................................ 115
8.1.2 Block Diagram...................................................................................................... 116
8.1.3 Pin Configuration ................................................................................................. 117
8.1.4 Register Configuration ......................................................................................... 117
8.1.5 Address Map ........................................................................................................ 118
8.2 Description of Registers .................................................................................................... 122
iii
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