|
|
PDF HMP8112 Data sheet ( Hoja de datos )
| Número de pieza | HMP8112 | |
| Descripción | NTSC/PAL Video Decoder | |
| Fabricantes | Harris | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HMP8112 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Semiconductor
March 1998
NOT RECOMMESNeDeEHDMFPO81R1N5EW DESIGNS
HMP8112
NTSC/PAL Video Decoder
Features
Description
• Supports ITU-R BT.601 (CCIR601) and Square Pixel
• 3 Composite Analog Inputs with Sync Tip AGC, Black
Clamping and White Peak Control
• Patented Decoding Scheme with Improved 2-Line
Comb Filter, Y/C Separation
• NTSC M, N, and PAL (B, D, G, H, I, M, N, CN) Operation
• Composite or S-Video Input
• User-Selectable Color Trap and Low Pass Video
Filters
• User Selectable Hue, Saturation, Contrast, Sharpness,
and Brightness Controls
• User Selectable Data Transfer Output Modes
- 16-Bit 4:2:2 YCbCr
- 8-Bit 4:2:2 YCbCr
• User Selectable Clock Range from 20MHz - 30MHz
• I2C Interface
• VMI Compatible Video Data Bus
Applications
• Multimedia PCs
• Video Conferencing
• Video Editing
• Video Security Systems
• Settop Boxes (Cable, Satellite, and Telco)
• Digital VCRs
• Related Products
- NTSC/PAL Encoders: HMP8154, HMP8156,
HMP8171, HMP8173
- NTSC/PAL Decoders: HMP8115
The HMP8112 is a high quality, digital video, color decoder with
internal A/D converters. The A/D function includes a 3:1 analog
input mux, Sync Tip AGC, Black clamping and two 8-bit A/D
Converters. The high quality A/D converters minimize pixel jitter
and crosstalk.
The decoder function is compatible with NTSC M, PAL B, D,
G, H, I, M, N and special combination PAL N video stan-
dards. Both composite (CVBS) and S-Video (Y/C) input for-
mats are supported. A 2 line comb filter plus a user
selectable Chrominance trap filter provide high quality Y/C
separation. Various adjustments are available to optimize
the image such as Brightness, Contrast, Saturation, Hue and
Sharpness controls. Video synchronization is achieved with
a 4xfSC chroma burst lock PLL for color demodulation and
line lock PLL for correct pixel alignment. A chrominance sub-
sampling 4:2:2 scheme is provided to reduce chrominance
bandwidth.
The HMP8112 is ideally suited as the analog video interface
to VCR’s and camera’s in any multimedia or video system.
The high quality Y/C separation, user flexibility and inte-
grated phase locked loops are ideal for use with today’s pow-
erful compression processors. The HMP8112 operates from
a single 5V supply and is TTL/CMOS compatible.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.NO.
HMP8112CN
0 to 70 80 Ld PQFP† Q80.14x20
HMP8112EVAL2 PCI Reference Design (Includes Part)
HMP8156EVAL2 Frame Grabber Evaluation Board
(Includes Part)
† PQFP is also known as QFP and MQFP
Table of Contents
Page
Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Operation Introduction. . . . . . . . . . . . . . . . . . . 6
Internal Register Description Tables . . . . . . . . . . . . . . . . . 14
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC and DC Electrical Specifications . . . . . . . . . . . . . . . . . 24
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . 27
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 4221.3
1 page  
HMP8112
Functional Block Diagrams (Continued)
ADDRESS
POINTER
ADDRESS
POINTER
CONTROL
REGISTERS
....
....
....
....
CONTROL
DATA BUS
0
1
.
.
.
.
25
CbCr[7:0]
SERIAL SHIFT
REGISTER
Y[7:0]
A0 SCL SDA
I2C CONTROL INTERFACE
OEN
32 X 16
DEEP
FIFO
8/16 OUTPUT
SELECT
R
E
G
I
S
T
E
R
8
R
E
M
U
X
G
I
S
T
8
E
R
OUTPUT INTERFACE
CbCr[7:0]
Y[7:0]
DVLD
ACTIVE
Schematic
LUMA0
LUMA1
LUMA2
U1
C3
1.0µF
5 LIN2
C5
1.0µF
C4
1.0µF
6 LIN1
7 LIN0
R3 R4 R5
75 75 75 LOW PASS FILTER
CRCB7 51 CR_CB7
CRCB6 50 CR_CB6
CRCB5 49 CR_CB5
CRCB4 48 CR_CB4
CRCB3 47 CR_CB3
CRCB2 45 CR_CB2
CRCB1 43 CR_CB1
CR_CB10. .71
CR_CB10. .71
CHROMA
R6
75
C6
1.0µF
R7
680
C2
15pF
L1
82µH
C1
15pF
19
CIN
9 L_OUT
8 L_ADIN
R8
5.62K
CRCB0 42 CR_CB0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
64
63
60
58
57
56
55
54
ACTIVE 65
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y10. .71
Y10. .71
VCC VCC VCC VCC VCC VCC VCC
R11 R12 R13 R14 R15 R16
10K 10K 10K 10K 10K 4K
R17
4K
ACTIVE
C9
0.22µF
C8
0.01µF
C7
0.01µF
77 DVLD 66
76
29
LAGC_CAP
LCLAMP_CAP
CCLAMP_CAP
FIELD
HSYNC
VSYNC
67
71
70
27
WPE
DVLD
FIELD
HDRIVE
VDRIVE
AVCC
28
GAIN_CNTL
RESET 34
SDA 40
41
SCL
RESET
SDA
SCL
R1
1K
C10 R9
78
DEC_T
30
DEC_L
C11 C12
38
CLK
13
CLK
36
TEST
VCC
27MHz
R10
50
C13
27MHz
0.1µF
0.1µF 0.1µF
5K
R18
R2 15pF
10K
10
JP1
JUMPER
5
5 Page 
HMP8112
The 2-bit values allow 4 choices of scaling factors. The
sharpness control helps to compensate for losses in the
scaling interpolators that can reduce the amplitude of high
frequency components.
TABLE 4. SHARPNESS GAIN FACTOR SELECTS
XF1 XF0
GAIN FACTOR
00
SCALED BY 1.0
01
SCALED BY 2.0
10
SCALED BY 4.0
11
SCALED BY 0
I 2C Control Interface
The HMP8112 utilizes an I2C control bus interface to pro-
gram the internal configuration registers. This standard
mode (up to 100 KBPS) interface consists of the bidirec-
tional Serial Data Line (SDA) and the Serial Clock Line
(SCL). The implementation on the HMP8112 is a simple
slave interface that will not respond to general calls and can-
not initiate a transfer. When the device is not active, the SDA
and SCL control pins should be pulled high through external
4kΩ pullup resistors.
+5V +5V +5V
The Color Killer
(AGC Hysteresis and Loop Limits)
HMP8112
VIDEO
DECODER
4kΩ 4kΩ
The color killer will disable the color difference path and set
the U and V components to zero. The automatic color killer
circuitry uses the AGC threshold to determine the maximum
and minimum gain factor limits. The loop filter determines
how much the AGC gain factor can be changed within one
line. The maximum gain factor (Max = 8) and the minimum
gain factor (Min = 0.5) will limit the range of the AGC. When
the gain factor exceeds the maximum gain factor of 8, the
gain factor is limited to 8. Once the signal has an amplitude
of 1/16th, the nominal video the color killer is enabled and
the chroma phase locked loop holds it’s last phase refer-
ence. While the color killer is enabled, the U and V compo-
nents are forced to zero. Once the input video signal reaches
1/7th the optimum amplitude the color killer is disabled and
the color is returned.
UV
DATA
÷4096
MAX
GAIN
FACTOR
MIN
GAIN
FACTOR
COLOR
KILLER
AGC
GAIN
FACTOR
I2C
LINE
COUNT
AGC
ENABLE
FIGURE 11. LOOP FILTER BLOCK DIAGRAM (HYSTERESIS)
The dynamic range of the AGC allows it to compensate for
video that is 1/8 to 2 times the specified nominal of 1VP-P.
41 40
SDA
SCL
FIGURE 12. PULLUP RESISTOR CONFIGURATION
The I2C clock/data timing is shown below in Figure 13. The
HMP8112 contains 29 internal registers used to program and
configure the Decoder. The I2C control port contains a pointer
register that auto-increments through the entire register space
and can be written. The autoincrement pointer will wrap after
the last register has been accessed (Product ID Register) and
should be set to the desired starting address each time an
access is started. For a write transfer, the I2C device base
address is the first part of a serial transfer. Then the internal
register pointer is loaded. Then a series of registers can be
written. If multiple registers are written, the pointer register will
autoincrement up through the register address space. A stop
cycle is used to end the transfer after the desired number of
registers are programmed.
For a read transfer, the I2C device address is the first part of
the serial transfer. Then the internal register pointer is
loaded. At this point another start cycle is initiated to access
the individual registers. Figure 14 shows the programming
flow for read transfer of the internal registers. Multiple regis-
ters can be read and the pointer register will autoincrement
up through the pointer register address space. On the last
data read, an acknowledge should not be issued. A stop
cycle is used to end the transfer after the desired number of
registers are read.
Saturation
The color saturation component is controlled via the Color
Saturation Registers. The color saturation is applied to the
UV components after the AGC function. The saturation value
is multiplied by the UV data to increase the color intensity.
The data range is from 0 to 1.96875 where 1.96875 is the
brightest intensity. This is an 8-bit number in the form:
X.XXX XXXX
The default value after a RESET is 1.2074 (9DH).
Product ID Register
The HMP8112 contains a product ID register that can be
used to identify the presence of a board during a Plug ’n Play
detection software algorithm. The Product ID code is 12H
and the register is the last register in the HMP8112 (1BH).
Output Data Port Modes
The HMP8112 can output data in 2 formats, an 8-bit Burst
mode and a 16-bit Synchronous Pixel Transfer mode. In 16-bit
Synchronous Pixel Transfer Mode pixel data is output at the
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HMP8112.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HMP8112 | NTSC/PAL Video Decoder | Harris |
| HMP8115 | NTSC/PAL Video Decoder |  Intersil Corporation |
| HMP8115CN | NTSC/PAL Video Decoder | Intersil Corporation |
| HMP8116 | NTSC/PAL Video Decoder | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |